Le7920
Data Sheet
ELECTRICAL CHARACTERISTICS (continued)
Description
Loop Detector
Test Conditions (See Note 1)
Min
Typ
Max
Unit
Note
On threshold
Off threshold
Hysteresis
RD = 35.4 kΩ
RD = 35.4 kΩ
RD = 35.4 kΩ
11.5
9.4
0
17.3
14.1
4.4
mA
Relay Driver Output (RINGOUT, RYOUT1, RYOUT2, RYOUT3)
On voltage
Off leakage
Zener breakover
Zener On voltage
IOL = 40 mA
VOH = +5 V
IZ = 100 µA
IZ = 30 mA
+0.3
+0.7
100
V
µA
6
7.2
10
V
RELAY DRIVER SCHEMATICS
RINGOUT
RYOUT1, RYOUT2, RYOUT3
BGND
BGND
Notes:
1. Unless otherwise noted, test conditions are BAT = –52 V, V
= +5 V, R = 600 Ω, R
= R
DC2
= 27.17 kΩ, R
= 2350 Ω,
CC
= 0.1 µF, C = 0.33 µF, D1 = 1N400x, two-wire AC input impedance is a 600 Ω
CAS
L
DC1
TMG
R
= 35.4 kΩ, no fuse resistors, C
= 0.22 µF, C
D
HP
DC
resistance synthesized by the programming network shown below.
VTX
RT1 = 75 kΩ
CT1 = 120 pF
RT2 = 75 kΩ
RSN
RRX = 150 kΩ
VRX
2. a. Overload level is defined when THD = 1%.
b. Overload level is defined when THD = 1.5%.
3. Balance return signal is the signal generated at V by V . This specification assumes that the two-wire, AC-load impedance matches
TX RX
the programmed impedance.
4. Not tested in production. This parameter is guaranteed by characterization or correlation to other tests.
5. This parameter is tested at 1 kHz in production. Performance at other frequencies is guaranteed by characterization.
6. Tested with 0 Ω source impedance. 2 MΩ is specified for system design only.
7. Group delay can be greatly reduced by using a ZT network such as that shown in Note 1. The network reduces the group delay to less than
2 µs and increases 2WRL. The effect of group delay on linecard performance also may be compensated for by synthesizing complex
impedance with the QSLAC™ or DSLAC™ device.
8. Minimum current level guaranteed not to cause a false loop detect.
10
Zarlink Semiconductor Inc.
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
