Le75183
Table 8. Additional Electrical Characteristics
Parameter
Digital Input Characteristics:
Input Low Voltage
Input High Voltage
Input Leakage Current (high)
Input Leakage Current (low)
Input Leakage Current (high)
INTESTOUT, INRING
Input Leakage Current (low)
INTESTOUT, INRING
Input Leakage Current (high)
INTESTIN, LATCH
Input Leakage Current (low)
INTESTIN, LATCH
Temperature Shutdown Requirements*:
Shutdown Activation Temperature
Shutdown Circuit Hysteresis
—
—
—
—
110
10
125
—
—
—
V
DD
= 5.5 V, V
BAT
= –75 V,
Vlogicin = 5 V
V
DD
= 5.5 V, V
BAT
= –75 V,
Vlogicin = 0 V
V
DD
= 5.5 V, V
BAT
= –58 V,
Vlogicin = 5 V
V
DD
= 5.5 V, V
BAT
= –58 V,
Vlogicin = 0 V
V
DD
= 5.5 V, V
BAT
= –58 V,
Vlogicin = 5 V
V
DD
= 5.5 V, V
BAT
= –58 V,
Vlogicin = 0 V
—
—
llogicin
llogicin
llogicin
llogicin
llogicin
llogicin
—
2.2
—
—
—
—
—
—
—
—
—
—
0.5
100
100
0.5
Test Condition
Measure
Min
Typ
Data Sheet
Max
0.8
—
500
500
—
µA
—
—
—
Unit
V
V
150
25
°C
°C
*Temperature shutdown flag (TSD) will be HIGH during normal operation and LOW during temperature shutdown state.
ZERO CROSS CURRENT TURN OFF
The ring access switch (SW8) is designed to turn off on the next zero current crossing after application of the appropriate logic
input control. This switch requires a current zero cross to turn off. Switch 8, once on, will remain in the ON state (regardless of
logic input) until a current zero cross. Therefore, to ensure proper operation of switch 8, this switch should be connected, via
proper impedance, to the ringing generator or some other ac source. Do not attempt to switch pure DC with switch 8. The ringing
test access switch, SW6, also has similar characteristics to switch 8 and should also only be used to switch signals with zero
current crossings.
For a detailed explanation of the operation of switches 6 and 8, please refer to the
An Introduction to Le758X Series of Line Card
Access Switches
application note.
SWITCHING BEHAVIOR
When switching from the power ringing state to the idle/talk state via simple logic level input control, the Le75183 is able to provide
control with respect to the timing when the ringing access contacts are released relative to the state of the line break contacts.
Make-before-break operation occurs when the line break switch contacts are closed (or made) before the ringing access switch
contact is opened (or broken). Break-before-make operation occurs when the ringing access contact is opened (broke) before
the line break switch contacts are closed (made).
Using the logic level input pins INRING, INTESTin, and INTESTout, either make-before-break or break-before-make operation of
the Le75183 is easily achieved. The logic sequences for either mode of operation are given in Table 13 and Table 14. See the
Truth Tables (Table 16 and Table 17) for an explanation of logic states.
When using an Le75183 in the make-before-break mode, during the ring-to-idle transition, for a period of up to one-half the
ringing frequency, the ring break switch and the pnpn-type ring access switch can both be in the ON state. This is the maximum
time after the logic signal at INRING has transitioned that the ring access switch is waiting for the next zero current cross, so it
can close. During this interval, current that is limited to the dc break switch current-limit value will be source from the ring node
of the SLIC.
This current is presented to the internal protection circuit. If the SCR-type protector is used (A or C codes), if by random probability
the ring-to-idle transition occurs during a portion of the ring cycle when the ringing voltage exceeds the protection circuit SCR
turn-on voltage, and if current in excess of the SCR’s turn-on current is also available, the SCR may turn on. Once the SCR is
triggered on, if the SLIC is capable of supplying current in excess of the holding current, the SCR may be latched on by the SLIC.
The probability of this event depends on the characteristics of the given SLIC and of the holding current of the Le75183 A or C
device. The SCR hold current distribution is designed to be safely away from the test limit of 80 mA. The higher the distribution,
the lower the probability of the latch.
If this situation is of concern for a given board design, either use the A or C series device in the break-before-make mode
(eliminates the original 25 ms current pulse) or use a B or D series device (eliminates the SCR).
13
Zarlink Semiconductor Inc.
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