Le75183
Data Sheet
TESTin
Switches
Break
Switches
Ring Test
Switches
Ring
TESTout
INRING
INTESTin INTESTout
TSD
Switches Switches
1/Float1
1/Float1
1/Float1
1/Float1
1/Float1
1/Float1
1/Float1
1Float1
02
Off3
Off
0
0
0
1
1
0
1
1
0
0
1
0
1
1
0
1
0
1
0
0
0
1
1
1
Off
Off
On
Off
Off
On
Off
Off
Off
On
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
On
Off
Off
Off
Off
On4
Off
Off5
Off
Off6
On
Off7
Off
On8
Off
Off9, 10
Off
Off9
Off
Off9
Off
Don’t Care Don’t Care Don’t Care
Table 12 - Truth Table for the Le75183A/B Devices
1. If TSD is logic 1, the thermal shutdown mechanism is disabled. If TSD is floating, the thermal shutdown mechanism is active.
2. Forcing TSD to logic 0 overrides the logic input pins and forces an all OFF state.
3. Idle/Talk state.
4. TESTout state.
5. TESTin state
6. Power ringing state.
7. Ringing generator test state.
8. Simultaneous TESTout and TESTin state.
9. All OFF state.
10. Default power up state.
A parallel in/parallel out data latch is integrated into the Le75183A/B. Operation of the data latch is controlled by the
logic level input pin LATCH. The data input to the latch is the INPUT pin of the Le75183A/B, and the output of the
data latch is an internal node used for state control.
When the LATCH control pin is at logic 0, the data latch is transparent and data control signals flow directly from
INPUT, through the data latch to state control. Any changes in INPUT will be reflected in the state of the switches.
When the LATCH control pin is at logic 1, the data latch is active; the Le75183A/B will no longer react to changes at
the INPUT control pin. The state of the switches is now latched; that is, the state of the switches will remain as they
were when the LATCH input transitioned from logic 0 to logic 1. The switches will not respond to changes in INPUT
as long as LATCH is held high.
Note that the TSD input is not tied to the data latch. TSD is not affected by the LATCH input. TSD input will override
state control via INPUT and LATCH.
24
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