KESRX04
Pulse Generator
Variable Delay Line
RX CLK
4KB/S
(50% Duty Cycle)
OOK Input
Bit Error Rate
KESRX04 PCB
Wanted
Signal
433.92 MHz.
Signal Generator 1
N/C N/C RFin RFGND
GND
Vcc DATA PD N/C
Trigger
Buffer Amplifier
RFin
DATA
O/P
Interfering
Signal
Hydbrid
Combiner
433.82
MHz.
Signal Generator 2
Oscilloscope
DC PSU (3 to 6V)
Figure 5 Characterising the selectivityand interference rejection
Note :
1
2
3
Variable delay line used to equalise the propagation delay of the receiver.
Buffer amplifier used to drive the low impedance input of the Bit Error Ratio analyser.
High impedance (*10 probe) oscilloscope probe recommended.
25
20
15
10
5
Anti-jam circuit
connected
0
-5
-10
-15
-20
-25
-30
-35
-40
Anti-jam circuit
By-passed
-100 -90
-80
-70
-60
-50
-40
-30
-20
-10
0
10
Wanted Signal level (dBm) at 433.92MHz (4kB/s 50% duty cycle)
Figure 5a In-band interference rejection of the receiver
Note: Unmodulated interfering signal is 100kHz low side from wanted signal. Both signals are within the passband of the
receiver (ceramic filter)
10
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
