KESRX04
Functional Operation
Power Down
The PD pin, a tristate input, provides a 2 stage power down
for the receiver. The receiver is fully operational when the pin
is held high and is fully powered down when the pin is taken to
ground.
Status
PD0
PD1
PD2
PD Pin
Low (0V)
Vcc/2
High (Vcc)
Status
Receiver powered down
Crystal oscillator running
Receive mode
The AGC circuit comes into operation at input signals
greater than ~ -35dBm and reduces the RF amplifer gain by
6dB at an input signal level of ~ -25dBm. Since the AGC
operates on the mixer output signal level then the exact point
where the AGC comes into operation depends on the RF
amplifer to mixer matching circuits and RF amplifer gain.
IF interface
Unlike KESRX01 there is no internal integrated IF filter. This
is to provide a more flexible design and allows the system
designer to use a low IF or high IF up to 15MHz. Typically, a
10.7MHz Ceramic IF filter connected between IFOUT and IFIN
would be used together with an input RF SAW filter to give very
good image channel rejection. The choice of bandwidth for the
10.7MHz ceramic filter depends on frequency tolerancing of
the transmitter, receiver, data rate and component cost.
The IF filter drive, IFOUT, is a voltage drive with a 300 ohm
series resistance. This allows impedance matching to the
ceramic IF filter to be set by an external series resistor. A
10.7MHz ceramic filter with, typically, a 300 ohm input imped-
ance does not require an external matching resistor at IFOUT.
The input to the log amp, IFIN, is high impedance with an
internal 4Kohm shunt resistor. Impedance matching to the
output of the ceramic filter is achieved by an external shunt
resistor R9 between IFIN and IFDC1.
PD0 = Low.
None of the receiver circuits are functional. Current, Icc2,
is reduced to its lowest level, <50µA (Vcc applied). A longer
settling time (ts2) is required to restore full performance after
switching to receive mode, PD0 to PD2 (Figure 6).
PD1 = Vcc/2 or high impedance source (CMOS
tristate).
A non-receiving state with some critical circuits running
including the crystal oscillator. Current consumption, Icc1, is
reduced to about 330µA. When switching to the receive state,
PD1 to PD2 (Figure 6), data can start to be recovered within
1ms (ts3) for signals close to maximum sensitivity.
PD2 = High.
The receiver is fully functional ready to receive data.
Phase Lock Loop VCO
The local oscillator (LO) is a VCO locked to a crystal
reference by a phase lock loop (PLL). The VCO gain is
nominally 40MHz/Volt depending on the external varactor
used. The LO frequency is divided by 64 and fed into the
phase-frequency detector, where the reference frequency is
provided from the crystal oscillator. The phase detector output
current into the PLL loop filter is nominally
±30µA.
The max
loop filter bandwidth is 50kHz.
Conducted LO signals capable of being radiated from the
antenna of the complete receiver are suppressed to a level of
<-65dBm into 50ohms.
RF down-converter
An internal RF amplifier is designed to interface to an input
SAW filter with a maximum insertion loss of 3dB.
The RF amplifier gain is about 13dB at 460MHz when
matched into the mixer, while the RF amplifer noise figure is
about 4.5dB when fed from a 50 ohm source. The internal RF
amplifier is
conditionally stable
and feeds a double balanced
mixer through an external impedance matching circuit, RFOP
to MIXIP.
The AGC circuit monitors the mixer signal output level.
Control is fed back, applying AGC to the RF amplifier to prevent
overloading in the mixer and the generation of unwanted
distortion products. This also has the effect of reducing the
RSSI characteristic slope and extending its range of operation
by more than 20dB at high signal levels, compare Figure 9B
and Figure 9C.
The AGC circuit also applies mixer booster current to
improve the linearity of the mixer at high signal levels. This can
be confirmed by monitoring the current consumption of the
receiver with applied RF signal level Figure 9D.
6
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
