KESRX04
Notes:
1.
The Sensitivity of the test fixture Figure 12 is degraded by loading the input to RF amplifier with 50 ohms, lack of image
rejection and increasing the data filter bandwidth to 50kHz. Sensitivity is defined as the average signal level measured
at the input necessary to achieve a bit error ratio of 0.01 where the input signal is a return to zero pulse at 470MHz.,with
an average duty cycle of 50%, 20kB/s data rate with the receiver bandwidth set to 470kHz.
Peak RF input level, pin RFIN, to overload the demodulator with the AGC operating. Equivalent to +7dBm for 50 ohm
input impedance. Where the input signal is a return to zero pulse at 470MHz. with an average duty cycle of 50%.
20kB/s data rate with the receiver bandwidth set to 470kHz.
Sensitivity is defined as the average signal level measured at the input necessary to achieve a bit error ratio of 0.01 where
the input signal is a return to zero pulse with an average duty cycle of 50%, 1kB/s data rate. Equivalent to -103dBm for
50ohm input impedance. Does not include insertion loss of SAW filter at RF input but does include IF filter of 470kHz
3dB bandwidth and a data filter bandwidth of 5kHz. This equates closely to a measurement of tangential sensitivity.
The performance of the power down option PD1 to PD2 cannot be guaranteed below 3V for temperatures less than 0°C
Time taken for PLL lock voltage to achieve 90% transition point of the control signal and the VCO frequency to achieve
within 470kHz of the final frequency. The time taken to acquire PLL acquisition is governed by the PLL loop filter (C12,
C1 and R2) and the crystal oscillator components (XTAL1, C13 and C14). The dominant term for PLL aquistion is the start-
up time of the crystal oscillator circuit, provided the PLL loop filter settling time is much less than the crystal oscillator start-
up time. Figure 6 illustrates a suitable test setup for measuring the acquisition time of the PLL. The electrical
characterisation parameters are based on the following set of conditions:
Crystal Oscillator circuit
C13 = C14
=
15pF
XTAL 1
Freq.
6.6128 MHz.
ESR
15.3
Ω
L
85.36 mH
C0
1.83 pF
C1
6.8 fF
PLL loop filter
C12 = 1.5 nF,
C1 = 180pF
R1 = 10KΩ
6.
Local oscillator power fed back into 50ohm source at antenna input (RF input). Measured with RF input matching network
shown in Figure 11.
In-band interference rejection for an unmodulated interfering signal at 100kHz. low side from the wanted modulated signal
at 433.92MHz. to achieve a Bit Error Rate =0.01. Figure 5 illustrates a suitable test set-up for measuring the interference
rejection and selectivity of the receiver.
Wanted signal =
(1kB/s. 50% duty cycle)
Interfering signal =
(unmodulated)
-90dBm at 433.92MHz.
2.
3.
4.
5.
7.
-76dBm at 433.82MHz.
Interference rejection typically equals +14dBm.
i.e. in-band interfering signal is 14dBm above the wanted signal level at –90dBm.
8.
Actual intermediate frequency determined by choice of crystal and external ceramic filter.
5
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