KESRX04
Interference rejection (dB) = Interferer (dBm) - Wanted (dBm)
The interference rejection of the receiver for different
modulation schemes can be improved by:
•
Changing the value of C2.
Increasing the value of C2 will result in pulse stretching of
the recovered signal
Adjusting the comparator reference level (DSN) by offsetting
the internal reference (Figure 4) by a high value resistor
from the DSN pin to Vee and or the peak detector output.
(Figure 11).
Reducing the bandwidth of the data fillter, intermediate
frequency filter and or the noise reduction filter (L5 // C7).
Thebandwidth of the receiver must accommodate
tolerancing of the data, transmitter and receiver.
Increasing the value of AGC capacitor C8 to maintain the
level of the AGC control during the “OFF” period of the
wanted modulation signal. This will improve the interference
rejection of the receiver but increase the time to good data
from power-up PD0 to PD2. The application circuit Figure
11 has been optimised for time to good data.
i.e.
Fc
=
5 *
1
(
DataPulsewidth
)
The output from this filter, DF2, is directly coupled into the
inverting input of the data comparator with a fixed slice level
applied to the non-inverting input, DSN. A peak detector
recovers the signal amplitude on the capacitor.
Normally, the comparator reference level used is the internal
reference, a capacitor at Pin DSN serving to remove noise
pick-up. In order to fine tune the slice level for sensitivity,
squelch and optimum interference rejection the slice level can
be offset from the internal reference by a high value resistor
from the DSN pin to Vee and or the peak detector output
(Figure 11).
The data comparator (slicer) output, DATOP, is CMOS
compatible but is only capable of driving small capacitive
loads, <20pF, depending on data rate. Data output has the
inverted sense
of the input signal at DF2.
The output drive current is nominally
±30µA
so that a
system using high data rates or higher capacitive loads, e.g.
long track lengths, may need to incorporate a buffer transistor
to provide the necessary edge speeds to the following logic
circuits. The comparator has 20mV hysteresis built-in to
reduce edge chatter.
The sense of the squelch on the data output is
LOW
when
no signal is present. This may be confusing, as a
LOW
output
during the data burst also corresponds to the ‘ON’ period, i.e.
the MARK, of the RF OOK signal. However, it is the very first
pulse of the data signal which causes the DC restoration
capacitor of the anti-jamming circuit to charge to the correct
level appropriate to the final slice level. As a consequence of
this the very first pulse of the data transmission may be lost as
the receiver adapts to the incoming signal level.
•
•
•
Baseband
The RSSI output will contain wide band demodulated
noise and signals which are within the RF and IF filter pass
bands. An additional low pass data filter is therefore used to
improve overall sensitivity.
KESRX04 has an integrated second-order Sallen-Key
data filter whose characteristic is set by R10, R11, C5 and C6.
Figure 7 shows the connections and calculation for the -3dB
cut-off frequency and filter type, The cut-off frequency is
determined from the data rate and the level of pulse distortion
which can be tolerated. The data filter cut off frequency is
usually set at 3 to 5 times the minimum pulse width period.
RFOP MIXIP
IFOUT IFIN
IFFLT1
IFDC2
IFDC1 RSSI DETB DF0 DF1
IFFLT2
DF2
PEAK DET
PEAK
VCCRF
ANTI-JAM
LIM AMP
DATA
FILTER
DATA
SLICER
DATAOP
AGC
AGC
DIV 64
PFD
XTAL
OSC
LNA
DSN
100K
Vref
RFIN
VCO
VCO1
PD
VCC
LF
VEERF VCO2
XTAL2 XTAL1
VEE
Figure 4 block schematic of KESRX04
9
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
