KESRX04
90
80
70
Selectivity Response (dB)
Anti-jam
connected
60
50
40
30
20
10
0
-10
-20
431
431.5
432
432.5
433
433.5
434
434.5
435
435.5
436
Frequency Response (MHz.)
Anti-jam
By-passed
Figure 5b KESRX04 selectivity response
Note:
The action of the anti-jam circuit to centre the bandwidth of the receiver around the wanted modulated signal at 433.92MHz
KESRX04 PCB
PLL
Spectrum Analyser
PLL
N/C
N/C RFin RFGND
GND
Vcc DATA PD N/C
PLL
Oscilloscope 1
Power Down
Trigger
DC PSU (3 to 6V)
GND
Power Down
Switch
+/- 470KHz.
t
Figure 6 Characterising the PLL aquisition time from power-up
Note :
1
2
3
4
•
•
•
5.
High impedance (*10 probe) oscilloscope probe recommended
Loosely coupled antenna or high impedance FET probe recommended for the spectrum analyser measurement.
Time taken for PLL to achieve 90% of final voltage and the VCO within +/- 470kHz. of final frequency (423.33MHz.)
Power down switch operation.
PD0 = PD pin connected to GND, receiver fully powered down.
PD1 = PD pin open circuit or connected to Vcc/2, crystal oscillator running.
PD2 = PD pin connected to Vcc, receiver fully operational.
Spectrum analyser set to PLL lock frequency (423.33MHz), zero span 470kHz IF bandwidth, t sweep 20mS.
11
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
