P
R
E
L
I
M
I
N
A
R
Y
I
N
F
O
R
M
A
T
I
O
N
XpressFlow-2020 Series –
Ethernet Switch Chipset
2.1.2 Supported Memory Configurations
EA218E
8-Port 10Mb Ethernet Access Controller
Read/Write Chip Select and High Address Bits
Chip #3
Chip #2
Chip #1
Chip #0
L_A[19] /
RAM Chip # of RAM Total Buffer
L_WE[3]# L_OE[3]# L_WE[2]# L_OE[2]# L_WE[1]# L_OE[1]# L_WE[0]# L_OE[0]#
Size
Chips Memory Size
32k x 32
1
2
4
64k x 32
1
2
4
128k x32
1
2
256k x32
1
128k bytes
256k bytes
512k bytes
256k bytes
512k bytes
1M bytes
512k bytes
1M bytes
1M bytes
----
----
----
----
----
----
----
----
----
----
L_WE[0]# L_OE[0]#
L_WE[1]# L_OE[1]# L_WE[0]# L_OE[0]#
L_WE[3]# L_OE[3]# L_WE[2]# L_OE[2]# L_WE[1]# L_OE[1]# L_WE[0]# L_OE[0]#
----
----
----
----
----
----
----
----
----
----
L_WE[0]# L_OE[0]#
L_WE[1]# L_OE[1]# L_WE[0]# L_OE[0]#
L_WE[3]# L_OE[3]# L_WE[2]# L_OE[2]# L_WE[1]# L_OE[1]# L_WE[0]# L_OE[0]#
----
----
----
----
----
L_A[19]
----
----
----
----
----
----
----
----
L_WE[0]# L_OE[0]#
L_WE[1]# L_OE[1]# L_WE[0]# L_OE[0]#
----
----
L_WE[0]# L_OE[0]#
2.1.3 Bus Cycle Waveforms
L_CLK
L_ADSC#
L_CS#
L_A[19:2]
L_WE[3:0]#
L_BWE[3:0]#
L_OE[3:0]#
A1
A2
A3
A3+1
A3+2
A3+3
A4
A4+1
A4+2
A4+3
A5
A6
L_D[31:0] (Wr)
D1
D3
D3+1
D3+2
D3+3
D6
L_D[31:0] (Rd)
D2
D4
D4+1
D4+2
D4+3
D5
Typical Local Memory Access Operations
© 1998
Zarlink Semiconductor, Inc.
9
Rev.2.1 – February, 1999
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
