Data Sheet
October 2002
L8583D Line Card Access Switch
Application
(continued)
Table 16. Truth Table for L8583D
IN
RING
IN
TESTin
IN
TESTout
T
SD
5 V/Float
1
5 V/Float
1
5 V/Float
1
5 V/Float
1
5 V/Float
1
5 V/Float
1
5 V/Float
1
5 V/Float
1
0 V
2
TESTin
Switches
Off
Off
On
Off
Off
On
Off
Off
Off
Break
Switches
On
Off
Off
Off
Off
Off
Off
Off
Off
Ring Test
Switches
Off
Off
Off
Off
On
Off
Off
On
Off
Ring
Switches
Off
Off
Off
On
Off
Off
Off
Off
Off
TESTout
Switches
Off
3
On
4
Off
5
Off
6
Off
7
On
8
Off
9,10
On
11
Off
9
0V
0V
0V
0V
0V
5V
0V
5V
0V
5V
0V
0V
5V
5V
0V
0V
5V
5V
5V
0V
5V
5V
5V
5V
Don’t Care Don’t Care Don’t Care
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
If T
SD
= 5 V, the thermal shutdown mechanism is disabled. If T
SD
is floating, the thermal shutdown mechanism is active.
Forcing T
SD
to ground overrides the logic input pins and forces an all-off state.
Idle/talk state.
TESTout state.
TESTin state.
Power ringing state.
Ringing generator test state.
Simultaneous TESTout and TESTin state.
All-off state.
Device will power up in this state.
Simultaneous TESTout—ring test state.
A parallel in/parallel out data latch is integrated into the L8583D. Operation of the data latch is controlled by the
logic-level input pin LATCH. The data input to the latch is the INPUT pin of the L8583D and the output of the data
latch is an internal node used for state control.
When the LATCH control pin is at logic 0, the data latch is transparent and data control signals flow directly from
INPUT, through the data latch to state control. Any changes in INPUT will be reflected in the state of the switches.
When the LATCH control pin is at logic 1, the data latch is active; the L8583D will no longer react to changes at the
INPUT control pin. The state of the switches is now latched; that is, the state of the switches will remain as they
were when the LATCH input transitioned from logic 0 to logic 1. The switches will not respond to changes in INPUT
as long as LATCH is held high.
Note that the T
SD
input is not tied to the data latch. T
SD
is not affected by the LATCH input. T
SD
input will override
state control via INPUT and LATCH.
The input logic pins IN
RING
and IN
TESTOUT
have internal pull-up resistors. Input logic pins IN
TESTIN
and LATCH
have internal pull-down resistors. Thus, the device will power up into the disconnect state.
17
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