54HSC/T630
16-bit Data Word
Checkword
Bit
CB0
CB1
CB2
CB3
CB4
CB5
0
X
X
X
1
X
X
X
X
X
X
2
3
X
X
4
X
X
X
X
X
X
X
X
X
X
X
X
X
X
5
6
7
8
X
X
9
X
X
X
X
X
X
X
10
X
X
X
X
X
X
X
X
X
11
12
13
X
X
X
X
X
14
15
The six check bits are partly bits derived from the matrix of data bits as indicated by 'X' for each bit.
Table 3: Check Word Generation
Syndrome
Error
Code
CB0
CB1
CB2
CB3
CB4
CB5
Error Location
No
DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9 DB10 DB11 DB12 DB13 DB14 DB15 CB0 CB1 CB2 CB3 CB4 CB5 Error
L
L
H
L
H
H
L
H
L
L
H
H
H
L
L
L
H
H
L
L
H
H
L
H
L
H
L
H
L
H
H
L
L
H
L
H
H
L
H
L
L
H
H
H
L
L
L
H
L
L
H
H
H
L
L
H
L
H
H
L
L
H
H
L
H
L
H
L
H
L
H
L
H
H
L
L
H
L
L
H
H
H
L
L
H
L
H
H
L
L
H
H
L
H
L
L
L
H
H
H
H
H
H
L
H
H
H
H
H
H
L
H
H
H
H
H
H
L
H
H
H
H
H
H
L
H
H
H
H
H
H
L
H
H
H
H
H
H
Table 4: Error Syndrome Codes
APPLICATIONS
Although many semiconductor memories have separate
input and output pins, it is possible to design the error
detection and correction function using a single EDAC. EDAC
data and check bit pins function as inputs or outputs
dependent upon the state of control signals S0 and S1. It
becomes necessary to use wired AND logic, with fairly
complex timing system, to control the EDAC and data bus.
This scheme becomes difficult to implement both in terms of
board layout and timing. System performance is also
adversely affected, See Figure 2.
Optimised systems can be implemented using two EDAC’s
in parallel, One of the units is used strictly as an encoder
during the memory write cycle. Both controls S0 and Sl are
grounded, The encoder chip will generate the 6-bit check word
for memory storage along with the 16-bit data.
The second of the two EDAC’s will be used as a decoder
during the memory read cycle. This decoder chip requires
timing pulses for correct operation. Control S1 is set low and
S0 high as the memory read cycle begins. After the memory
output data is valid, the control S1 input is moved from the low
to a high. This low-to-high transition latches the 22-bit word
from memory into internal registers of this second EDAC and
enables the two error flags. If no error occurs, the CPU can
accept the 16-bit word directly from memory. If a single error
has occurred, the CPU must move the control SO input from
the high to a low to output corrected data and the error
syndrome bits. Any dual error should be an interrupt condition.
In most applications, status registers will be used to keep
tabs on error flags and error syndrome bits. If repeated
patterns of error flags and syndrome bits occur, the CPU will
be able to recognize these symptoms as a “hard” error. The
syndrome bits can be used to pinpoint the faulty memory chip,
See Figure 3.
Figure 2: Error Detection and Correction Using a
Single EDAC Unit
3
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