R
Spartan-II FPGA Family: Pinout Tables
XC2S50 Device Pinouts (Continued)
Additional XC2S50 Package Pins
XC2S50 Pad Name
TQ144
Bndry
Scan
Not Connected Pins
Function
Bank TQ144
PQ208
-
FG256
D8
P104
P105
-
-
-
-
I/O
I/O
0
0
0
-
-
83
86
89
-
11/02/00
-
P188
P189
P190
P191
P192
P193
P194
P195
P196
P197
A6
I/O, VREF
GND
I/O
P12
B7
-
GND*
C8
0
0
0
0
0
-
-
-
92
95
98
104
107
-
I/O
D7
I/O
-
E7
I/O
P11
P10
P9
-
C7
I/O
B6
VCCINT
VCCO
VCCINT*
0
VCCO
-
Bank 0*
GND
I/O
-
P8
P7
P6
-
P198
P199
P200
P201
-
GND*
A5
-
0
0
0
0
0
0
-
110
113
116
119
122
125
-
I/O
C6
I/O
B5
I/O
-
D6
I/O
-
P202
P203
-
A4
I/O, VREF
GND
I/O
P5
-
B4
GND*
E6
0
0
0
0
0
-
-
P204
-
128
131
134
137
140
-
I/O
-
D5
I/O
P4
-
P205
-
A3
I/O
C5
I/O
P3
P2
P1
P206
P207
P208
B3
TCK
VCCO
C4
0
VCCO
-
Bank 0*
VCCO
7
P144
P208
VCCO
-
Bank 7*
04/18/01
Notes:
1. IRDY and TRDY can only be accessed when using Xilinx PCI
cores.
2. Pads labelled GND*, VCCINT*, VCCO Bank 0*, VCCO Bank 1*,
VCCO Bank 2*, VCCO Bank 3*, VCCO Bank 4*, VCCO Bank 5*,
VCCO Bank 6*, VCCO Bank 7* are internally bonded to
independent ground or power planes within the package.
3. See "VCCO Banks" for details on VCCO banking.
DS001-4 (v2.8) June 13, 2008
Product Specification
www.xilinx.com
Module 4 of 4
80
XILINX [ XILINX, INC ]
