R
Spartan and Spartan-XL Families Field Programmable Gate Arrays
T
PWDW
PWRDWN
50 ns
50 ns
Power Down Mode
Outputs
Description
Min
Symbol
T
50 ns
Power Down Time
PWD
T
Power Down Pulse Width
50 ns
PWDW
DS060_23_041901
Figure 23: PWRDWN Pulse Timing
Power-down retains the configuration, but loses all data
stored in the device flip-flops. All inputs are interpreted as
Low, but the internal combinatorial logic is fully functional.
Make sure that the combination of all inputs Low and all
flip-flops set or reset in your design will not generate internal
oscillations, or create permanent bus contention by activat-
ing internal bus drivers with conflicting data onto the same
long line.
configuration bit defines the state of a static memory cell
that controls either a function look-up table bit, a multiplexer
input, or an interconnect pass transistor. The Xilinx develop-
ment system translates the design into a netlist file. It auto-
matically partitions, places and routes the logic and
generates the configuration data in PROM format.
Configuration Mode Control
During configuration, the PWRDWN pin must be High. If the
Power Down state is entered before or during configuration,
the device will restart configuration once the PWRDWN sig-
nal is removed. Note that the configuration pins are affected
by Power Down and may not reflect their normal function. If
there is an external pull-up resistor on the DONE pin, it will
be High during Power Down even if the device is not yet
configured. Similarly, if PWRDWN is asserted before config-
uration is completed, the INIT pin will not indicate status
information.
5V Spartan devices have two configuration modes.
•
•
MODE = 1 sets Slave Serial mode
MODE = 0 sets Master Serial mode
3V Spartan-XL devices have three configuration modes.
•
•
•
M1/M0 = 11 sets Slave Serial mode
M1/M0 = 10 sets Master Serial mode
M1/M0 = 0X sets Express mode
In addition to these modes, the device can be configured
through the Boundary Scan logic (See "Configuration
Through the Boundary Scan Pins" on page 37.).
Note that the PWRDWN pin is not part of the Boundary
Scan chain. Therefore, the Spartan-XL family has a sepa-
rate set of BSDL files than the 5V Spartan family. Boundary
scan logic is not usable during Power Down.
The Mode pins are sampled prior to starting configuration to
determine the configuration mode. After configuration,
these pin are unused. The Mode pins have a weak pull-up
resistor turned on during configuration. With the Mode pins
High, Slave Serial mode is selected, which is the most pop-
ular configuration mode. Therefore, for the most common
configuration mode, the Mode pins can be left unconnected.
If the Master Serial mode is desired, the MODE/M0 pin
should be connected directly to GND, or through a
pull-down resistor of 1 KΩ or less.
Configuration and Test
Configuration is the process of loading design-specific pro-
gramming data into one or more FPGAs to define the func-
tional operation of the internal blocks and their
interconnections. This is somewhat like loading the com-
mand registers of a programmable peripheral chip.
Spartan/XL devices use several hundred bits of configura-
tion data per CLB and its associated interconnects. Each
DS060 (v1.6) September 19, 2001
Product Specification
www.xilinx.com
1-800-255-7778
25
XILINX [ XILINX, INC ]
