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XCS40XL-4PQ240C 参数 Datasheet PDF下载

XCS40XL-4PQ240C图片预览
型号: XCS40XL-4PQ240C
PDF下载: 下载PDF文件 查看货源
内容描述: 斯巴达和Spartan-XL系列现场可编程门阵列 [Spartan and Spartan-XL Families Field Programmable Gate Arrays]
分类和应用: 现场可编程门阵列可编程逻辑时钟
文件页数/大小: 82 页 / 848 K
品牌: XILINX [ XILINX, INC ]
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Spartan and Spartan-XL Families Field Programmable Gate Arrays  
Over Operating Conditions" on page 43.). This high value  
makes them unsuitable as wired-AND pull-up resistors.  
falling-edge or rising-edge triggered flip-flops. The clock  
inputs for each IOB are independent.  
Common Clock Enables  
Table 7: Supported Destinations for Spartan/XL  
Outputs  
The input and output flip-flops in each IOB have a common  
clock enable input (see EC signal in Figure 5), which  
through configuration, can be activated individually for the  
input or output flip-flop, or both. This clock enable operates  
exactly like the EC signal on the Spartan/XL CLB. It cannot  
be inverted within the IOB.  
Spartan-XL  
Outputs  
Spartan  
Outputs  
5V,  
5V,  
Destination  
Any device,  
= 3.3V,  
3.3V, CMOS  
TTL  
CMOS  
(1)  
Some  
Routing Channel Description  
V
CC  
All internal routing channels are composed of metal seg-  
ments with programmable switching points and switching  
matrices to implement the desired routing. A structured,  
hierarchical matrix of routing channels is provided to  
achieve efficient automated routing.  
CMOS-threshold  
inputs  
Any device,  
V
= 5V,  
CC  
TTL-thresholdinputs  
This section describes the routing channels available in  
Spartan/XL devices. Figure 8 shows a general block dia-  
gram of the CLB routing channels. The implementation soft-  
ware automatically assigns the appropriate resources  
based on the density and timing requirements of the design.  
The following description of the routing channels is for infor-  
mation only and is simplified with some minor details omit-  
ted. For an exact interconnect description the designer  
should open a design in the FPGA Editor and review the  
actual connections in this tool.  
Any device,  
Unreliable  
Data  
V
= 5V,  
CC  
CMOS-threshold  
inputs  
Notes:  
1. Only if destination device has 5V tolerant inputs.  
After configuration, voltage levels of unused pads, bonded  
or unbonded, must be valid logic levels, to reduce noise  
sensitivity and avoid excess current. Therefore, by default,  
unused pads are configured with the internal pull-up resistor  
active. Alternatively, they can be individually configured with  
the pull-down resistor, or as a driven output, or to be driven  
by an external source. To activate the internal pull-up, attach  
the PULLUP library component to the net attached to the  
pad. To activate the internal pull-down, attach the PULL-  
DOWN library component to the net attached to the pad.  
The routing channels will be discussed as follows;  
CLB routing channels which run along each row and  
column of the CLB array.  
IOB routing channels which form a ring (called a  
VersaRing) around the outside of the CLB array. It  
connects the I/O with the CLB routing channels.  
Global routing consists of dedicated networks primarily  
designed to distribute clocks throughout the device with  
minimum delay and skew. Global routing can also be  
used for other high-fanout signals.  
Set/Reset  
As with the CLB registers, the GSR signal can be used to  
set or clear the input and output registers, depending on the  
value of the INIT attribute or property. The two flip-flops can  
be individually configured to set or clear on reset and after  
configuration. Other than the global GSR net, no user-con-  
trolled set/reset signal is available to the I/O flip-flops  
(Figure 5). The choice of set or reset applies to both the ini-  
tial state of the flip-flop and the response to the GSR pulse.  
CLB Routing Channels  
The routing channels around the CLB are derived from  
three types of interconnects; single-length, double-length,  
and longlines. At the intersection of each vertical and hori-  
zontal routing channel is a signal steering matrix called a  
Programmable Switch Matrix (PSM). Figure 8 shows the  
basic routing channel configuration showing single-length  
lines, double-length lines and longlines as well as the CLBs  
and PSMs. The CLB to routing channel interface is shown  
as well as how the PSMs interface at the channel intersec-  
tions.  
Independent Clocks  
Separate clock signals are provided for the input (IK) and  
output (OK) flip-flops. The clock can be independently  
inverted for each flip-flop within the IOB, generating either  
10  
www.xilinx.com  
1-800-255-7778  
DS060 (v1.6) September 19, 2001  
Product Specification