R
Platform Flash In-System Programmable Configuration PROMs
Programming
The Platform Flash PROM is a reprogrammable NOR flash
device (refer
for the program/erase specifications).
Reprogramming requires an erase followed by a program
operation. A verify operation is recommended after the
program operation to validate the correct transfer of data
from the programmer source to the Platform Flash PROM.
Several programming solutions are available.
V
CC
In-System Programming
GND
In-System Programmable PROMs can be programmed
individually, or two or more can be daisy-chained together and
programmed in-system via the standard 4-pin JTAG protocol
as shown in
In-system programming offers quick
and efficient design iterations and eliminates unnecessary
package handling or socketing of devices. The programming
data sequence is delivered to the device using either Xilinx
iMPACT software and a Xilinx download cable, a third-party
JTAG development system, a JTAG-compatible board tester,
or a simple microprocessor interface that emulates the JTAG
instruction sequence. The iMPACT software also outputs
serial vector format (SVF) files for use with any tools that
accept SVF format, including automatic test equipment.
During in-system programming, the CEO output is driven
High. All other outputs are held in a high-impedance state or
held at clamp levels during in-system programming.
In-system programming is fully supported across the
recommended operating voltage and temperature ranges.
(a)
(b)
DS026_02_082703
Figure 3:
JTAG In-System Programming Operation
(a) Solder Device to PCB
(b) Program Using Download Cable
External Programming
Xilinx reprogrammable PROMs can also be programmed by
the Xilinx MultiPRO Desktop Tool or a third-party device
programmer. This provides the added flexibility of using
pre-programmed devices with an in-system programmable
option for future enhancements and design changes.
Reliability and Endurance
Xilinx in-system programmable products provide a
guaranteed endurance level of 20,000 in-system
program/erase cycles and a minimum data retention of 20
years. Each device meets all functional, performance, and
data retention specifications within this endurance limit.
OE/RESET
The 1/2/4 Mbit XCFxxS Platform Flash PROMs in-system
programming algorithm results in issuance of an internal
device reset that causes OE/RESET to pulse Low.
DS123 (v2.11.1) March 30, 2007
Product Specification
5
XILINX [ XILINX, INC ]
