R
Platform Flash In-System Programmable Configuration PROMs
devices are to be configured with the same bitstream,
readback is not being used, and the CCLK frequency
selected does not require the use of the BUSY signal, the
CS_B pins can be connected to a common line so all of the
devices are configured simultaneously (Figure
With additional control logic, the individual devices can be
loaded separately by asserting the CS_B pin of each device
in turn and then enabling the appropriate configuration data.
The PROM can also store the individual bitstreams for each
FPGA for SelectMAP configuration in separate design
revisions. When design revisioning is utilized, additional
control logic can be used to select the appropriate bitstream
by asserting the EN_EXT_SEL pin, and using the
REV_SEL[1:0] pins to select the required bitstream, while
asserting the CS_B pin for the FPGA the bitstream is
targeting (Figure
For clocking the parallel configuration chain, either the first
FPGA in the chain can be set to Master SelectMAP,
generating the CCLK, with the remaining devices set to
Slave SelectMAP, or all the FPGA devices can be set to
Slave SelectMAP and an externally generated clock can be
used to drive the configuration interface. Again, the
respective device data sheets should be consulted for
detailed information on a particular FPGA device, including
which configuration modes are supported by the targeted
FPGA device.
CCLK. If BUSY is asserted (High) by the FPGA, the
configuration data must be held until BUSY goes Low. An
external data source or external pull-down resistors must be
used to enable the FPGA's active Low Chip Select (CS or
CS_B) and Write (WRITE or RDWR_B) signals to enable the
FPGA's SelectMAP configuration process.
After configuration, the pins of the SelectMAP port can be
used as additional user I/O. Alternatively, the port can be
retained using the persist option.
Connecting the FPGA device to the configuration PROM for
Slave SelectMAP (Parallel) Configuration Mode (Figure
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The DATA outputs of the PROM(s) drives the [D0..D7]
inputs of the lead FPGA device.
The PROM CLKOUT (for XCFxxP only) or an external
clock source drives the FPGA's CCLK input.
The CEO output of a PROM drives the CE input of the
next PROM in a daisy chain (if any).
The OE/RESET pins of all PROMs are connected to
the INIT_B pins of all FPGA devices. This connection
assures that the PROM address counter is reset before
the start of any (re)configuration.
The PROM CE input can be driven from the DONE pin.
The CE input of the first (or only) PROM can be driven
by the DONE output of all target FPGA devices,
provided that DONE is not permanently grounded. CE
can also be permanently tied Low, but this keeps the
DATA output active and causes an unnecessary I
CC
active supply current ("DC
For high-frequency parallel configuration, the BUSY
pins of all PROMs are connected to the FPGA's BUSY
output (when the FPGA has a BUSY pin and when the
use of the FPGA BUSY pin is required). This
connection assures that the next data transition for the
PROM is delayed until the FPGA is ready for the next
configuration data byte. For FPGA BUSY pin
requirements, refer to the appropriate FPGA data sheet
or FPGA family configuration user guide.
The PROM CF pin is typically connected to the FPGA's
PROG_B (or PROGRAM) input. For the XCFxxP only,
the CF pin is a bidirectional pin. If the XCFxxP CF pin is
not connected to the FPGA's PROG_B (or PROGRAM)
input, then the pin should be tied High.
•
Cascading Configuration PROMs
When configuring multiple FPGAs in a serial daisy chain,
configuring multiple FPGAs in a SelectMAP parallel chain,
or configuring a single FPGA requiring a larger
configuration bitstream, cascaded PROMs provide
additional memory (Figure
and
Multiple
Platform Flash PROMs can be concatenated by using the
CEO output to drive the CE input of the downstream device.
The clock signal and the data outputs of all Platform Flash
PROMs in the chain are interconnected. After the last data
from the first PROM is read, the first PROM asserts its CEO
output Low and drives its outputs to a high-impedance
state. The second PROM recognizes the Low level on its CE
input and immediately enables its outputs.
After configuration is complete, address counters of all
cascaded PROMs are reset if the PROM OE/RESET pin
goes Low or CE goes High.
When utilizing the advanced features for the XCFxxP
Platform Flash PROM, including the clock output (CLKOUT)
option, decompression option, or design revisioning,
programming files which span cascaded PROM devices
can only be created for cascaded chains containing only
XCFxxP PROMs. If the advanced features are not used,
then cascaded PROM chains can contain both XCFxxP and
XCFxxS PROMs.
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FPGA SelectMAP (Parallel) Device Chaining
(XCFxxP PROM Only)
Multiple Virtex-II FPGAs can be configured using the
SelectMAP mode, and be made to start up simultaneously.
To configure multiple devices in this way, wire the individual
CCLK, DONE, INIT, Data ([D0..D7]), Write (WRITE or
RDWR_B), and BUSY pins of all the devices in parallel. If all
DS123 (v2.11.1) March 30, 2007
Product Specification
14
XILINX [ XILINX, INC ]
