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Platform Flash In-System Programmable Configuration PROMs
PROM to FPGA Configuration Mode and Connections Summary
The FPGA's I/O, logical functions, and internal
interconnections are established by the configuration data
contained in the FPGA’s bitstream. The bitstream is loaded
into the FPGA either automatically upon power up, or on
command, depending on the state of the FPGA's mode pins.
Xilinx Platform Flash PROMs are designed to download
directly to the FPGA configuration interface. FPGA
configuration modes which are supported by the XCFxxS
Platform Flash PROMs include: Master Serial and Slave
Serial. FPGA configuration modes which are supported by
the XCFxxP Platform Flash PROMs include: Master Serial,
Slave Serial, Master SelectMAP, and Slave SelectMAP.
Below is a short summary of the supported FPGA
configuration modes. See the respective FPGA data sheet
for device configuration details, including which configuration
modes are supported by the targeted FPGA device.
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The PROM CE input can be driven from the DONE pin.
The CE input of the first (or only) PROM can be driven
by the DONE output of all target FPGA devices,
provided that DONE is not permanently grounded. CE
can also be permanently tied Low, but this keeps the
DATA output active and causes an unnecessary I
CC
active supply current ("DC
The PROM CF pin is typically connected to the FPGA's
PROG_B (or PROGRAM) input. For the XCFxxP only,
the CF pin is a bidirectional pin. If the XCFxxP CF pin is
not connected to the FPGA's PROG_B (or PROGRAM)
input, then the pin should be tied High.
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FPGA Slave Serial Mode
In Slave Serial mode, the FPGA loads the configuration
bitstream in bit-serial form from external memory synchronized
by an externally supplied clock. Upon power-up or
reconfiguration, the FPGA's mode select pins are used to
select the Slave Serial configuration mode. Slave Serial Mode
provides a simple configuration interface. Only a serial data
line, a clock line, and two control lines (INIT and DONE) are
required to configure an FPGA. Data from the PROM is read
out sequentially on a single data line (DIN), accessed via the
PROM's internal address counter which is incremented on
every valid rising edge of CCLK. The serial bitstream data
must be set up at the FPGA’s DIN input pin a short time before
each rising edge of the externally provided CCLK.
Connecting the FPGA device to the configuration PROM for
Slave Serial Configuration Mode (Figure
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The DATA output of the PROM(s) drive the DIN input of
the lead FPGA device.
The PROM CLKOUT (for XCFxxP only) or an external
clock source drives the FPGA's CCLK input.
The CEO output of a PROM drives the CE input of the
next PROM in a daisy chain (if any).
The OE/RESET pins of all PROMs are connected to
the INIT_B (or INIT) pins of all FPGA devices. This
connection assures that the PROM address counter is
reset before the start of any (re)configuration.
The PROM CE input can be driven from the DONE pin.
The CE input of the first (or only) PROM can be driven
by the DONE output of all target FPGA devices,
provided that DONE is not permanently grounded. CE
can also be permanently tied Low, but this keeps the
DATA output active and causes an unnecessary I
CC
active supply current ("DC
The PROM CF pin is typically connected to the FPGA's
PROG_B (or PROGRAM) input. For the XCFxxP only,
the CF pin is a bidirectional pin. If the XCFxxP CF pin is
not connected to the FPGA's PROG_B (or PROGRAM)
input, then the pin should be tied High.
FPGA Master Serial Mode
In Master Serial mode, the FPGA automatically loads the
configuration bitstream in bit-serial form from external
memory synchronized by the configuration clock (CCLK)
generated by the FPGA. Upon power-up or reconfiguration,
the FPGA's mode select pins are used to select the Master
Serial configuration mode. Master Serial Mode provides a
simple configuration interface. Only a serial data line, a
clock line, and two control lines (INIT and DONE) are
required to configure an FPGA. Data from the PROM is
read out sequentially on a single data line (DIN), accessed
via the PROM's internal address counter which is
incremented on every valid rising edge of CCLK. The serial
bitstream data must be set up at the FPGA’s DIN input pin a
short time before each rising edge of the FPGA's internally
generated CCLK signal.
Typically, a wide range of frequencies can be selected for
the FPGA’s internally generated CCLK which always starts
at a slow default frequency. The FPGA’s bitstream contains
configuration bits which can switch CCLK to a higher
frequency for the remainder of the Master Serial
configuration sequence. The desired CCLK frequency is
selected during bitstream generation.
Connecting the FPGA device to the configuration PROM for
Master Serial Configuration Mode (Figure
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The DATA output of the PROM(s) drive the DIN input of
the lead FPGA device.
The Master FPGA CCLK output drives the CLK input(s)
of the PROM(s)
The CEO output of a PROM drives the CE input of the
next PROM in a daisy chain (if any).
The OE/RESET pins of all PROMs are connected to
the INIT_B pins of all FPGA devices. This connection
assures that the PROM address counter is reset before
the start of any (re)configuration.
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DS123 (v2.11.1) March 30, 2007
Product Specification
12
XILINX [ XILINX, INC ]
