XC9572XL High Performance CPLD
application note
125
178 MHz
100
Typical ICC (mA)
Hi g
hP
rm
erfo
anc
e
R
75
50
Low
w
Po
er
104 MHz
25
0
50
100
150
200
Clock Frequency (MHz)
DS057_01_010102
Figure 1:
Typical I
CC
vs. Frequency for XC9572XL
3
JTAG Port
1
JTAG
Controller
In-System Programming Controller
54
I/O
I/O
I/O
18
Function
Block 1
Macrocells
1 to 18
Fast CONNECT II Switch Matrix
I/O
54
18
Function
Block 2
Macrocells
1 to 18
I/O
Blocks
I/O
I/O
I/O
I/O
3
I/O/GCK
1
I/O/GSR
I/O/GTS
2
54
18
Function
Block 3
Macrocells
1 to 18
54
18
Function
Block 4
Macrocells
1 to 18
DS057_02_082800
Figure 2:
XC9572XL Architecture
Function Block outputs (indicated by the bold line) drive the I/O Blocks directly.
2
DS057 (v2.0) April 3, 2007
Product Specification
XILINX [ XILINX, INC ]
