R
XC95144XL High Performance CPLD
Internal Timing Parameters
XC95144XL-5
XC95144XL-7
XC95144XL-10
Symbol
Parameter
Min
Max
Min
Max
Min
Max
Units
Buffer Delays
TIN
Input buffer delay
GCK buffer delay
-
-
-
-
-
-
1.5
1.1
2.0
4.0
2.0
0
-
-
-
-
-
-
2.3
1.5
3.1
5.0
2.5
0
-
-
-
-
-
-
3.5
1.8
4.5
7.0
3.0
0
ns
ns
ns
ns
ns
ns
TGCK
TGSR
TGTS
TOUT
TEN
GSR buffer delay
GTS buffer delay
Output buffer delay
Output buffer enable/disable
delay
Product Term Control Delays
TPTCK Product term clock delay
TPTSR Product term set/reset delay
-
-
-
1.6
1.0
5.5
-
-
-
2.4
1.4
7.2
-
-
-
2.7
1.8
7.5
ns
ns
ns
TPTTS
Product term 3-state delay
Internal Register and Combinatorial Delays
TPDI
TSUI
THI
Combinatorial logic propagation delay
Register setup time
-
2.3
1.4
2.3
1.4
-
0.5
-
2.6
2.2
2.6
2.2
-
1.3
-
3.0
3.5
3.0
3.5
-
1.7
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
-
-
-
-
-
-
Register hold time
TECSU Register clock enable setup time
TECHO Register clock enable hold time
-
-
-
-
-
-
TCOI
TAOI
Register clock to output valid time
Register async. S/R to output delay
Register async. S/R recover before clock
Internal logic delay
0.4
6.0
0.5
6.4
1.0
7.0
-
-
-
TRAI
5.0
-
7.5
-
10.0
-
TLOGI
1.0
5.0
1.4
6.4
1.8
7.3
TLOGILP Internal low power logic delay
-
-
-
Feedback Delays
TF
Fast CONNECT II feedback delay
-
1.9
-
3.5
-
4.2
ns
Time Adders
TPTA
Incremental product term allocator delay
-
-
0.7
3.0
-
-
0.8
4.0
-
-
1.0
4.5
ns
ns
TSLEW Slew-rate limited delay
6
www.xilinx.com
DS056 (v2.0) April 3, 2007
Product Specification
XILINX [ XILINX, INC ]
