XC6VSX475T-1FFG1156I 参数 Datasheet PDF下载

型号：	XC6VSX475T-1FFG1156I
PDF下载：	下载PDF文件查看货源
内容描述：	[Field Programmable Gate Array, 1098MHz, 476160-Cell, CMOS, PBGA1156, 35 X 35 MM, LEAD FREE, FBGA-1156]
分类和应用：	时钟栅可编程逻辑
文件页数/大小：	65 页 / 1429 K
品牌：	XILINX [ XILINX, INC ]

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Virtex-6 FPGA Data Sheet: DC and Switching Characteristics

Table 45: IOB Switching Characteristics for the Defense-grade (XQ) Virtex-6 Devices (Cont’d)

T_IOPI

Speed Grade

-1

T_IOOP

Speed Grade

-1

T_IOTP

Speed Grade

-1

I/O Standard

Units

-2

-1L

-2

-1L

-2

-1L

LVDCI_DV2_18

LVDCI_DV2_15

LVPECL_25

0.61

0.73

0.94

0.91

0.94

0.91

0.94

0.72

0.85

1.09

1.06

1.09

1.06

1.09

0.73

0.85

1.08

1.06

1.08

1.06

1.08

1.81

1.77

1.49

1.60

1.50

1.49

1.50

1.45

1.53

1.46

1.53

1.54

1.58

1.53

1.56

1.50

1.62

1.46

1.53

1.56

1.49

1.53

1.50

1.53

1.58

1.50

1.51

1.47

1.51

1.52

1.60

1.53

1.54

1.50

1.53

1.58

1.51

2.36

2.30

2.68

2.48

2.43

2.39

2.43

2.48

2.44

2.41

2.43

2.50

2.30

2.21

2.28

2.33

2.18

2.22

2.29

2.26

2.51

2.50

2.52

2.48

2.46

2.49

2.41

2.49

2.48

2.34

2.25

2.29

2.23

2.26

2.22

2.30

1.98

1.64

1.74

1.64

1.66

1.64

1.61

1.66

1.59

1.66

1.67

1.72

1.66

1.71

1.64

1.78

1.59

1.66

1.72

1.66

1.68

1.69

1.68

1.73

1.66

1.65

1.62

1.65

1.66

1.74

1.68

1.71

1.69

1.68

1.73

1.65

1.81

1.77

1.49

1.60

1.50

1.49

1.50

1.45

1.53

1.46

1.53

1.54

1.58

1.53

1.56

1.50

1.62

1.46

1.53

1.56

1.49

1.53

1.50

1.53

1.58

1.50

1.51

1.47

1.51

1.52

1.60

1.53

1.54

1.50

1.53

1.58

1.51

2.36

2.30

2.68

2.48

2.43

2.39

2.43

2.48

2.44

2.41

2.43

2.50

2.30

2.21

2.28

2.33

2.18

2.22

2.29

2.26

2.51

2.50

2.52

2.48

2.46

2.49

2.41

2.49

2.48

2.34

2.25

2.29

2.23

2.26

2.22

2.30

1.98

1.64

1.74

1.64

1.66

1.64

1.61

1.66

1.59

1.66

1.67

1.72

1.66

1.71

1.64

1.78

1.59

1.66

1.72

1.66

1.68

1.69

1.68

1.73

1.66

1.65

1.62

1.65

1.66

1.74

1.68

1.71

1.69

1.68

1.73

1.65

HSTL_I_12

HSTL_I_DCI

HSTL_II_DCI

HSTL_II_T_DCI

HSTL_III_DCI

HSTL_I_DCI_18

HSTL_II_DCI_18

HSTL_II _T_DCI_18

HSTL_III_DCI_18

DIFF_HSTL_I_18

DIFF_HSTL_I_DCI_18

DIFF_HSTL_I

DIFF_HSTL_I_DCI

DIFF_HSTL_II_18

DIFF_HSTL_II_DCI_18

DIFF_HSTL_II _T_DCI_18

DIFF_HSTL_II

DIFF_HSTL_II_DCI

SSTL2_I_DCI

SSTL2_II_DCI

SSTL2_II_T_DCI

SSTL18_I

SSTL18_II

SSTL18_I_DCI

SSTL18_II_DCI

SSTL18_II_T_DCI

SSTL15_T_DCI

SSTL15_DCI

DIFF_SSTL2_I

DIFF_SSTL2_I_DCI

DIFF_SSTL2_II

DIFF_SSTL2_II_DCI

DIFF_SSTL2_II_T_DCI

DIFF_SSTL18_I

DIFF_SSTL18_I_DCI

DS152 (v3.6) March 18, 2014

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