Spartan-6 Family Overview
Input/Output
The number of I/O pins varies from 102 to 576, depending on device and package size. Each I/O pin is configurable and can
comply with a large number of standards, using up to 3.3V. The
Spartan-6 FPGA SelectIO Resources User Guide
describes
the I/O compatibilities of the various I/O options. With the exception of supply pins and a few dedicated configuration pins,
all other package pins have the same I/O capabilities, constrained only by certain banking rules. All user I/O is bidirectional;
there are no input-only pins.
All I/O pins are organized in banks, with four banks on the smaller devices and six banks on the larger devices. Each bank
has several common V
CCO
output supply-voltage pins, which also powers certain input buffers. Some single-ended input
buffers require an externally applied reference voltage (V
REF
). There are several dual-purpose V
REF
-I/O pins in each bank.
In a given bank, when I/O standard calls for a V
REF
voltage, each V
REF
pin in that bank must be connected to the same
voltage rail and can not be used as an I/O pin.
I/O Electrical Characteristics
Single-ended outputs use a conventional CMOS push/pull output structure, driving High towards V
CCO
or Low towards
ground, and can be put into high-Z state. Many I/O features are available to the system designer to optionally invoke in each
I/O in their design, such as weak internal pull-up and pull-down resistors, strong internal split-termination input resistors,
adjustable output drive-strengths and slew-rates, and differential termination resistors. See the
Spartan-6 FPGA SelectIO
Resources User Guide
for more details on available options for each I/O standard.
I/O Logic
Input and Output Delay
This section describes the available logic resources connected to the I/O interfaces. All inputs and outputs can be configured
as either combinatorial or registered. Double data rate (DDR) is supported by all inputs and outputs. Any input or output can
be individually delayed by up to 256 increments of ~100 ps each. This is implemented as IODELAY2. The identical delay
value is available either for data input or output. For a bidirectional data line, the transfer from input to output delay is
automatic. The number of delay steps can be set by configuration and can also be incremented or decremented while in use.
Because these tap delays vary with supply voltage, process, and temperature, an optional calibration mechanism is built into
each IODELAY2:
•
•
In the simple system synchronous case, a data input delay value that guarantees zero data hold time is inserted
automatically, without user intervention.
For source synchronous designs where more accuracy is required, the calibration mechanism can (optionally)
determine dynamically how many taps are needed to delay data by one full I/O clock cycle, and then programs the
IODELAY2 with 50% of that value, thus centering the I/O clock in the middle of the data eye.
A special mode is available only for differential inputs, which uses a phase-detector mechanism to determine whether
the incoming data signal is being accurately sampled in the middle of the eye. The results from the phase-detector logic
can be used to either increment or decrement the input delay, one tap at a time, to ensure error-free operation at very
high bit rates.
•
ISERDES and OSERDES
Many applications combine high-speed bit-serial I/O with slower parallel operation inside the device. This requires a
serializer and deserializer (SerDes) inside the I/O structure. Each input has access to its own deserializer (serial-to-parallel
converter) with programmable parallel width of 2, 3, or 4 bits. Where differential inputs are used, the two serializers can be
cascaded to provide parallel widths of 5, 6, 7, or 8 bits. Each output has access to its own serializer (parallel-to-serial
converter) with programmable parallel width of 2, 3, or 4 bits. Two serializers can be cascaded when a differential driver is
used to give access to bus widths of 5, 6, 7, or 8 bits.
When distributing a double data rate clock, all SerDes data is actually clocked in/out at single data rate to eliminate the
possibility of bit errors due to duty cycle distortion. This faster single data rate clock is either derived via frequency
multiplication in a PLL, or doubled locally in each IOB by differentiating both clock edges when the incoming clock uses
double data rate.
DS160 (v1.4) March 3, 2010
Advance Product Specification
7
XILINX [ XILINX, INC ]
