Spartan-6 Family Overview
Spartan-6 FPGA Feature Summary
Table 1:
Spartan-6 FPGA Feature Summary by Device
Configurable Logic Blocks (CLBs)
Device
Logic
Cells
(1)
Slices
(2)
Max
Flip-Flops Distributed
RAM (Kb)
DSP48A1
Slices
(3)
Block RAM Blocks
18 Kb
(4)
CMTs
(5)
Max (Kb)
Memory
Endpoint
Maximum
Total Max
Controller
Blocks for
GTP
I/O
User
Blocks
PCI Express Transceivers Banks I/O
(Max)
XC6SLX4
XC6SLX9
XC6SLX16
XC6SLX25
XC6SLX45
XC6SLX75
XC6SLX100
XC6SLX150
XC6SLX25T
XC6SLX45T
XC6SLX75T
XC6SLX100T
XC6SLX150T
3,840
9,152
14,579
24,051
43,661
74,637
101,261
147,443
24,051
43,661
74,637
101,261
147,443
600
1,430
2,278
3,758
6,822
11,662
15,822
23,038
3,758
6,822
11,662
15,822
23,038
4,800
11,440
18,224
30,064
54,576
93,296
126,576
184,304
30,064
54,576
93,296
126,576
184,304
75
90
136
229
401
692
976
1,355
229
401
692
976
1,355
8
16
32
38
58
132
180
180
38
58
132
180
180
12
32
32
52
116
172
268
268
52
116
172
268
268
216
576
576
936
2,088
3,096
4,824
4,824
936
2,088
3,096
4,824
4,824
2
2
2
2
4
6
6
6
2
4
6
6
6
0
2
2
2
2
4
4
4
2
2
4
4
4
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
2
4
8
8
8
4
4
4
4
4
6
6
6
4
4
6
6
6
132
200
232
266
358
408
480
576
250
296
348
498
540
Notes:
1.
2.
3.
4.
5.
Spartan-6 FPGA logic cell ratings reflect the increased logic cell capability offered by the new 6-input LUT architecture.
Each Spartan-6 FPGA slice contains four LUTs and eight flip-flops.
Each DSP48A1 slice contains an 18 x 18 multiplier, an adder, and an accumulator.
Block RAMs are fundamentally 18 Kb in size. Each block can also be used as two independent 9 Kb blocks.
Each CMT contains two DCMs and one PLL.
DS160 (v1.4) March 3, 2010
Advance Product Specification
2
XILINX [ XILINX, INC ]
