R
Virtex-5 Family Overview
RocketIO GTP Transceivers (LXT/SXT only)
PowerPC 440 RISC Cores (FXT only)
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Full-duplex serial transceiver capable of 100 Mb/s to
3.75 Gb/s baud rates
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Embedded PowerPC 440 (PPC440) cores
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Up to 550 MHz operation
Greater than 1000 DMIPS per core
Seven-stage pipeline
Multiple instructions per cycle
Out-of-order execution
32 Kbyte, 64-way set associative level 1 instruction
cache
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8B/10B, user-defined FPGA logic, or no encoding
options
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Channel bonding support
CRC generation and checking
Programmable pre-emphasis or pre-equalization for
the transmitter
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32 Kbyte, 64-way set associative level 1 data cache
Book E compliant
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Programmable termination and voltage swing
Programmable equalization for the receiver
Receiver signal detect and loss of signal indicator
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Integrated crossbar for enhanced system performance
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128-bit Processor Local Buses (PLBs)
Integrated scatter/gather DMA controllers
Dedicated interface for connection to DDR2 memory
controller
User dynamic reconfiguration using secondary
configuration bus
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Auto-synchronization for non-integer PLB-to-CPU clock
ratios
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Out of Band (OOB) support for Serial ATA (SATA)
Electrical idle, beaconing, receiver detection, and PCI
Express and SATA spread-spectrum clocking support
Auxiliary Processor Unit (APU) Interface and Controller
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Direct connection from PPC440 embedded block to
FPGA fabric-based coprocessors
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Less than 100 mW typical power consumption
Built-in PRBS Generators and Checkers
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128-bit wide pipelined APU Load/Store
Support of autonomous instructions: no pipeline stalls
Programmable decode for custom instructions
RocketIO GTX Transceivers (TXT/FXT only)
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Full-duplex serial transceiver capable of 150 Mb/s to
6.5 Gb/s baud rates
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8B/10B encoding and programmable gearbox to
support 64B/66B and 64B/67B encoding, user-defined
FPGA logic, or no encoding options
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•
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Channel bonding support
CRC generation and checking
Programmable pre-emphasis or pre-equalization for
the transmitter
•
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Programmable termination and voltage swing
Programmable continuous time equalization for the
receiver
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Programmable decision feedback equalization for the
receiver
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Receiver signal detect and loss of signal indicator
User dynamic reconfiguration using secondary
configuration bus
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OOB support (SATA)
Electrical idle, beaconing, receiver detection, and
PCI Express spread-spectrum clocking support
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Low-power operation at all line rates
DS100 (v5.1) August 21, 2015
www.xilinx.com
Product Specification
5
XILINX [ XILINX, INC ]
