R
Virtex-5 Family Overview
Table 1: Virtex-5 FPGA Family Members
Configurable Logic Blocks (CLBs)
Block RAM Blocks
Max RocketIO
Endpoint
(6)
PowerPC
Processor
Blocks
Transceivers
Total
I/O
Max
DSP48E
Blocks for Ethernet
(4)
Device
Max
CMTs
User
(2)
(5)
Array
Virtex-5
Slices
Max
(Kb)
PCI
Express
MACs
(3)
(8)
(7)
Distributed
RAM (Kb)
18 Kb
36 Kb
Banks
I/O
(1)
(Row x Col) Slices
GTP
GTX
XC5VLX30
XC5VLX50
XC5VLX85
XC5VLX110
XC5VLX155
XC5VLX220
XC5VLX330
XC5VLX20T
XC5VLX30T
XC5VLX50T
XC5VLX85T
80 x 30
4,800
7,200
320
480
32
48
64
96
32
48
96
1,152
1,728
3,456
2
6
6
6
6
6
6
1
2
6
6
6
6
6
6
2
6
6
6
6
6
2
6
6
6
6
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
1
N/A
N/A
N/A
N/A
N/A
N/A
N/A
1
N/A
N/A
N/A
N/A
N/A
N/A
N/A
2
N/A
N/A
N/A
N/A
N/A
N/A
N/A
4
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
40
13
17
17
23
23
23
33
7
400
560
560
800
800
800
120 x 30
120 x 54 12,960
160 x 54 17,280
160 x 76 24,320
160 x 108 34,560
240 x 108 51,840
840
48
192
256
384
384
576
52
1,120
1,640
2,280
3,420
210
64
128 4,608
192 6,912
192 6,912
288 10,368
128
128
192
24
1,200
172
360
480
480
680
680
680
960
360
480
640
960
680
680
360
640
680
840
960
60 x 26
80 x 30
120 x 30
3,120
4,800
7,200
26
36
60
936
320
32
72
1,296
2,160
1
4
8
12
15
15
20
20
20
27
12
15
19
27
20
20
12
19
20
24
27
480
48
120
216
296
424
424
648
168
264
488
1
4
12
120 x 54 12,960
840
48
108 3,888
148 5,328
212 7,632
212 7,632
324 11,664
1
4
12
XC5VLX110T 160 x 54 17,280
XC5VLX155T 160 x 76 24,320
XC5VLX220T 160 x 108 34,560
XC5VLX330T 240 x 108 51,840
1,120
1,640
2,280
3,420
520
64
1
4
16
128
128
192
192
288
640
1
4
16
1
4
16
1
4
24
XC5VSX35T
XC5VSX50T
XC5VSX95T
80 x 34
5,440
8,160
84
3,024
1
4
8
120 x 34
780
132 4,752
244 8,784
1
4
12
160 x 46 14,720
1,520
4,200
1,500
2,400
380
1
4
16
XC5VSX240T 240 x 78 37,440
XC5VTX150T 200 x 58 23,200
XC5VTX240T 240 x 78 37,440
1,056 1,032 516 18,576
1
4
24
80
96
456
648
136
296
456
596
912
228 8,208
324 11,664
1
4
N/A
N/A
N/A
N/A
N/A
N/A
N/A
1
4
48
XC5VFX30T
XC5VFX70T
80 x 38
5,120
64
68
2,448
1
4
8
160 x 38 11,200
820
128
256
320
384
148 5,328
228 8,208
298 10,728
456 16,416
1
3
4
16
XC5VFX100T 160 x 56 16,000
XC5VFX130T 200 x 56 20,480
XC5VFX200T 240 x 68 30,720
1,240
1,580
2,280
2
3
4
16
2
3
6
20
2
4
8
24
Notes:
1. Virtex-5 FPGA slices are organized differently from previous generations. Each Virtex-5 FPGA slice contains four LUTs and four flip-flops (previously
it was two LUTs and two flip-flops.)
2. Each DSP48E slice contains a 25 x 18 multiplier, an adder, and an accumulator.
3. Block RAMs are fundamentally 36 Kbits in size. Each block can also be used as two independent 18-Kbit blocks.
4. Each Clock Management Tile (CMT) contains two DCMs and one PLL.
5. This table lists separate Ethernet MACs per device.
6. RocketIO GTP transceivers are designed to run from 100 Mb/s to 3.75 Gb/s. RocketIO GTX transceivers are designed to run from 150 Mb/s to
6.5 Gb/s.
7. This number does not include RocketIO transceivers.
8. Includes configuration Bank 0.
2
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DS100 (v5.1) August 21, 2015
Product Specification
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