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XC5VLX50-1FFG676I 参数 Datasheet PDF下载

XC5VLX50-1FFG676I图片预览
型号: XC5VLX50-1FFG676I
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 3600 CLBs, 1098MHz, 46080-Cell, CMOS, PBGA676, 27 X 27 MM, LEAD FREE, FBGA-676]
分类和应用: 可编程逻辑
文件页数/大小: 15 页 / 172 K
品牌: XILINX [ XILINX, INC ]
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R
Virtex-5 Family Overview  
Revision History  
The following table shows the revision history for this document.  
Date  
Version  
Revision  
04/14/06  
1.0  
Initial Xilinx release.  
First version posted to the Xilinx website. Minor typographical edits and description updates to highlight  
new features. Removed LUT utilization bullet from "Virtex-5 FPGA Logic," page 3.  
05/12/06  
1.1  
Added LXT platform to entire document. This includes descriptions of the RocketIO GTP transceivers,  
the Ethernet MACs, and the PCI Express Endpoint block.  
09/06/06  
10/12/06  
2.0  
2.1  
Added LX85T devices. Added System Monitor descriptions and functionality.  
Added LX220T devices. Revised the Total I/O banks for the LX330 in Table 1. Revised the  
XC5VLX50T-FFG665 example in Figure 1. Clarified support for "Differential SSTL 1.8V and 2.5V  
(Class I and II)," page 7.  
12/28/06  
2.2  
02/02/07  
05/23/07  
09/04/07  
12/11/07  
3.0  
3.1  
3.2  
3.3  
Added the SXT platform to entire document.  
Removed support for IEEE 1149.6  
Revised maximum line rate from 3.2 Gb/s to 3.75 Gb/s in entire document.  
Added LX20T, LX155T, and LX155 devices.  
Added Disclaimer. Revised CMT section on page 3. Clarified "Virtex-5 FPGA LogiCORE Endpoint  
Block Plus Wrapper for PCI Express," page 10.  
12/17/07  
3.4  
Added FXT platform to entire document.  
Clarified information in the following sections: "Integrated Endpoint Block for PCI Express Compliance"  
and "Tri-Mode Ethernet Media Access Controller."  
03/31/08  
4.0  
To avoid confusion with PLL functionality, removed PMCD references in "Global Clocking," page 8.  
04/25/08  
05/07/08  
4.1  
4.2  
Added XC5VSX240T to entire document.  
Updated throughout data sheet that the RocketIO GTX transceivers are designed to run from 150 Mb/s  
to 6.5 Gb/s.  
Clarified PPC440MC_DDR2 memory controller on page 5.  
Revised Ethernet MAC column in Table 1, page 2 and added Note 5. Also updated "Tri-Mode  
(10/100/1000 Mb/s) Ethernet MACs," page 9.  
06/18/08  
09/23/08  
4.3  
4.4  
Added TXT platform to entire document.  
Revised RocketIO GTX transciever datapath support on page 10.  
02/6/09  
5.0  
5.1  
Changed document classification to Product Specification from Advance Product Specification.  
Updated Table 2 and Figure 1 with RoHS package information.  
08/21/15  
DS100 (v5.1) August 21, 2015  
www.xilinx.com  
Product Specification  
13  
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