XC4000A Logic Cell Array Family
CLB Switching Characteristic Guidelines (continued)
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally
tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing patterns. The following
guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more precise, and more up-to-date
timing information, use the values provided by the XACT timing calculator and used in the simulator.
XC4003A
XC4005A
CLB RAM OPTION
Description
Write Operation
Address write cycle time
Write Enable pulse width (High)
Address set-up time before beginning of WE
Address hold time after end of WE
DIN set-up time before end of WE
DIN hold time after end of WE
Speed Grade
Symbol
16 x 2
32 x 1
16 x 2
32 x 1
16 x 2
32 x 1
16 x 2
32 x 1
16 x 2
32 x 1
both
T
WC
T
WCT
T
WP
T
WPT
T
AS
T
AST
T
AH
T
AHT
T
DS
T
DST
T
DHT
Min
-6
Max
-5
Min Max
8.0
8.0
4.0
4.0
2.0
2.0
2.0
2.0
4.0
5.0
2.0
-4
Min Max Units
8.0
8.0
4.0
4.0
2.0
2.0
2.0
2.0
4.0
5.0
2.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read Operation
Address read cycle time
Data valid after address change
(no Write Enable)
Read Operation, Clocking Data into Flip-Flop
Address setup time before clock K
Read During Write
Data valid after WE going active
(DIN stable before WE)
Data valid after DIN
(DIN change during WE)
Read During Write, Clocking Data into Flip-Flop
WE setup time before clock K
Data setup time before clock K
16 x 2
32 x 1
16 x 2
32 x 1
T
RC
T
RCT
T
ILO
T
IHO
7.0
10.0
6.0
8.0
5.5
7.5
4.5
7.0
5.0
7.0
PRELIMINARY
4.0
6.0
9.0
11.0
8.5
11.0
9.0
9.0
5.0
5.0
2.0
2.0
2.0
2.0
4.0
5.0
2.0
ns
ns
ns
ns
16 x 2
32 x 1
16 x 2
32 x 1
16 x 2
32 x 1
T
ICK
T
IHCK
T
WO
T
WOT
T
DO
T
DOT
6.0
8.0
12.0
15.0
11.0
14.0
4.5
6.0
10.0
12.0
9.0
11.0
4.5
6.0
ns
ns
ns
ns
ns
ns
16 x 2
32 x 1
16 x 2
32 x 1
T
WCK
T
WCKT
T
DCK
T
DCKT
12.0
15.0
11.0
14.0
10.0
12.0
9.0
11.0
9.5
11.5
9.0
11.0
ns
ns
ns
ns
Note: Timing for the 16 x 1 RAM option is identical to 16 x 2 RAM timing
2-78
XILINX [ XILINX, INC ]
