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XC4002A 参数 Datasheet PDF下载

XC4002A图片预览
型号: XC4002A
PDF下载: 下载PDF文件 查看货源
内容描述: 逻辑单元阵列系列 [Logic Cell Array Family]
分类和应用:
文件页数/大小: 16 页 / 100 K
品牌: XILINX [ XILINX, INC ]
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CLB Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally
tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing patterns. The following
guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more precise, and more up-to-date
timing information, use the values provided by the XACT timing calculator and used in the simulator.
XC4003A
XC4005A
Speed Grade
Description
Combinatorial Delays
F/G inputs to X/Y outputs
F/G inputs via H' to X/Y outputs
C inputs via H' to X/Y outputs
CLB Fast Carry Logic
Operand inputs (F1,F2,G1,G4) to C
OUT
Add/Subtract input (F3) to C
OUT
Initialization inputs (F1,F3) to C
OUT
C
IN
through function generators to X/Y outputs
C
IN
to C
OUT
, bypass function generators.
Sequential Delays
Clock K to outputs Q
Set-up Time before Clock K
F/G inputs
F/G inputs via H'
C inputs via H1
C inputs via DIN
C inputs via EC
C inputs via S/R, going Low (inactive)
C
IN
input via F'/G'
C
IN
input via F'/G' and H'
Hold Time after Clock K
F/G inputs
F/G inputs via H'
C inputs via H1
C inputs via DIN
C inputs via EC
C inputs via S/R, going Low (inactive)
Clock
Clock High time
Clock Low time
Set/Reset Direct
Width (High)
Delay from C inputs via S/R, going High to Q
Master Set/Reset*
Width (High or Low)
Delay from Global Set/Reset net to Q
Symbol
-6
Min Max
-5
Min
Max
-4
Min Max Units
T
ILO
T
IHO
T
HHO
6.0
8.0
7.0
4.5
7.0
5.0
4.0
6.0
4.5
ns
ns
ns
T
CKO
5.0
3.0
PRELIMINARY
3.0
7.0
28.0
T
OPCY
T
ASCY
T
INCY
T
SUM
T
BYP
7.0
8.0
6.0
8.0
2.0
5.5
6.0
4.0
6.0
1.5
5.0
5.5
3.5
5.5
1.5
ns
ns
ns
ns
ns
ns
T
ICK
T
IHCK
T
HHCK
T
DICK
T
ECCK
T
RCK
6.0
8.0
7.0
4.0
7.0
6.0
8.0
10.0
4.5
6.0
5.0
3.0
4.0
4.5
6.0
7.5
4.5
6.0
5.0
3.0
3.0
4.0
5.5
7.3
ns
ns
ns
ns
ns
ns
ns
ns
T
CKI
T
CKIH
T
CKHH
T
CKDI
T
CKEC
T
CKR
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ns
ns
ns
ns
ns
ns
T
CH
T
CL
5.0
5.0
4.0
4.0
4.0
4.0
ns
ns
T
RPW
T
RIO
5.0
9.0
4.0
8.0
4.0
ns
ns
T
MRW
T
MRQ
21.0
33.0
18.0
31.0
18.0
ns
ns
* Timing is based on the XC4005. For other devices see XACT timing calculator.
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