XC4000, XC4000A, XC4000H Logic Cell Array Families
The XACT system also includes XDelay, a static timing
analyzer. XDelay examines a design’s logic and timing to
calculate the performance along signal paths, identify pos-
sible race conditions, and detect set-up and hold-time
violations. Timing analyzers do not require that the user
generate input stimulus patterns or test vectors.
Summary
The result of eight years of FPGA design experience and
feedback from thousands of customers, the XC4000 families
combine architectural versatility, on-chip RAM, increased
speed and gate complexity with abundant routing resources
and new, sophisticated software to achieve fully automated
implementation of complex, high-performance designs.
Multiplexers
4
13
m2-1e
m4-1e
m8-1e
m16-1e
Registers
rd4r
rd8r
rd16r
Shift Registers
sr8ce
sr16re
RAMs
ram 16x4
2
4
8
2
4
8
1
1
3
5
7400 Equivalents
‘138
‘139
‘147
‘148
‘150
‘151
‘152
‘153
‘154
‘157
‘158
‘160
‘161
‘162
‘163
‘164
‘165s
‘166
‘168
‘174
‘194
‘195
‘280
‘283
‘298
‘352
‘390
‘518
‘521
# of CLBs
5
2
5
6
5
3
3
2
16
2
2
5
6
8
8
4
9
5
7
3
5
3
3
8
2
2
3
3
3
Barrel Shifters
brlshft4
brlshft8
4-Bit Counters
cd4ce
cd4cle
cd4rle
cb4ce
cb4cle
cb4re
8- and 16-Bit Counters
cb8ce
cb8re
cc16ce
cc16cle
cc16cled
Identity Comparators
comp4
comp8
comp16
Magnitude Comparators
compm4
compm8
compm16
Decoders
d2-4e
d3-8e
d4-16e
2
4
16
4
9
20
1
2
5
6
10
10
11
21
3
5
6
3
6
5
Explanation of counter nomenclature
cb =
cd =
cc =
d =
l =
x =
e =
r =
c =
binary counter
BCD counter
cascadable binary counter
bidirectional
loadable
cascadable
clock enable
synchronous reset
asynchronous clear
Figure 10. CLB Count of Selected XC4000 Soft Macros
2-18
XILINX [ XILINX, INC ]
