R
Functional Description
A specific Spartan-3E part type always requires a constant
number of configuration bits, regardless of design complex-
ity, as shown in Table 39. The configuration file size for a
multiple-FPGA daisy-chain design equals the sum of the
individual file sizes.
Pin Behavior During Configuration
Table 40 shows how various pins behave during the FPGA
configuration process. The actual behavior depends on the
values applied to the M2, M1, and M0 mode select pins and
the HSWAP pin. The mode select pins determine which of
the I/O pins are borrowed during configuration and how they
function. In JTAG configuration mode, no user-I/O pins are
borrowed for configuration.
Table 39: Number of Bits to Program a Spartan-3E
FPGA (Uncompressed Bitstreams)
All I/O pins are high impedance (floating, three-stated, Hi-Z)
during the configuration process. These pins are indicated
in Table 40 as shaded table entries or cells. If the HSWAP
input is Low, these pins have a pull-up resistor to their asso-
ciated VCCO supply that is active throughout configuration.
After configuration, pull-up and pull-down resistors are
available in the FPGA application as described in Pull-Up
and Pull-Down Resistors, page 9.
Number of Configuration
Device
Bits
XC3S100E
XC3S250E
XC3S500E
XC3S1200E
XC3S1600E
581,344
1,352,192
2,267,136
3,832,320
5,957,760
Spartan-3E FPGAs have only six dedicated configuration
pins, including the DONE and PROG_B pins, and the four
JTAG boundary-scan pins: TDI, TDO, TMS, and TCK.
Table 40: Pin Behavior during Configuration
Master
Serial
SPI (Serial BPI(Parallel
Slave
Parallel
Supply/
I/O Bank
Pin Name
TDI
Flash)
NOR Flash)
JTAG
TDI
Slave Serial
TDI
TMS
TCK
TDO
PROG_B
DONE
HSWAP
0
TDI
TDI
TDI
TMS
TCK
TDO
PROG_B
DONE
HSWAP
1
TDI
TMS
TCK
TDO
PROG_B
DONE
HSWAP
1
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
0
TMS
TMS
TCK
TDO
PROG_B
DONE
HSWAP
0
TMS
TMS
TCK
TDO
PROG_B
DONE
HSWAP
1
TCK
TCK
TDO
TDO
PROG_B
DONE
HSWAP
M2
PROG_B
DONE
HSWAP
0
2
M1
0
0
1
0
1
1
2
M0
0
1
0 = Up
1
0
1
2
1 = Down
CCLK
INIT_B
CSO_B
DOUT/BUSY
MOSI/CSI_B
D7
CCLK (O)
INIT_B
CCLK (O)
INIT_B
CSO_B
DOUT
CCLK (O)
INIT_B
CSO_B
BUSY
CSI_B
D7
CCLK (I)
INIT_B
CSO_B
BUSY
CSI_B
D7
CCLK (I)
INIT_B
2
2
2
2
2
2
2
2
2
DOUT
DOUT
MOSI
D6
D6
D6
D5
D5
D5
D4
D4
D4
DS312-2 (v1.1) March 21, 2005
www.xilinx.com
57
Advance Product Specification
XILINX [ XILINX, INC ]
