R
Pinout Descriptions
FG484
Table 31: FG484 Package Pinout
Table 31: FG484 Package Pinout
XC3S1600E
FG484
Ball
XC3S1600E
Bank
Pin Name
Type
Bank
Pin Name
Ball
M13
N10
N12
N14
P13
Type
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
K9
K11
K13
L10
L11
L12
L14
M9
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
User I/Os by Bank
Table 32 indicates how the 304 available user-I/O pins are
distributed between the four I/O banks on the FG484 pack-
age.
M11
M12
Table 32: User I/Os Per Bank for the XC3S1600E in the FG484 Package
All Possible I/O Pins by Type
Package
Edge
Maximum
I/O
I/O Bank
I/O
56
INPUT
DUAL
1
VREF
GCLK
Top
0
1
2
3
94
94
22
16
18
16
72
7
7
8
0
Right
50
21
24
0
Bottom
Left
94
45
7
0
94
63
7
8
TOTAL
376
214
46
28
16
Footprint Migration Differences
The XC3S1600E FPGA is the only Spartan-3E device
offered in the FG484 package.
DS312-4 (v1.1) March 21, 2005
www.xilinx.com
69
Advance Product Specification
XILINX [ XILINX, INC ]
