R
DC and Switching Characteristics
TCCH
TCCL
TCK
(Input)
1/FTCK
TTCKTMS
TTMSTCK
TMS
(Input)
TTDITCK
TTCKTDI
TDI
(Input)
TTCKTDO
TDO
(Output)
DS099_06_040703
Figure 6: JTAG Waveforms
Table 19: Timing for the JTAG Test Access Port
All Speed Grades
Symbol
Description
Min
Max
Units
Clock-to-Output Times
TTCKTDO
The time from the falling transition on the TCK pin
to data appearing at the TDO pin
1.0
11.0
ns
Setup Times
TTDITCK
The time from the setup of data at the TDI pin to
the rising transition at the TCK pin
7.0
7.0
-
-
ns
ns
TTMSTCK
The time from the setup of a logic level at the TMS
pin to the rising transition at the TCK pin
Hold Times
TTCKTDI
The time from the rising transition at the TCK pin
to the point when data is last held at the TDI pin
0
0
-
-
ns
ns
TTCKTMS
The time from the rising transition at the TCK pin
to the point when a logic level is last held at the
TMS pin
Clock Timing
TCCH
The High pulse width at the TCK pin
The Low pulse width at the TCK pin
Frequency of the TCK signal
5
5
-
-
-
ns
ns
TCCL
FTCK
33
MHz
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 4.
DS312-3 (v1.0) March 1, 2005
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17
Advance Product Specification
XILINX [ XILINX, INC ]
