R
DC and Switching Characteristics
Table 18: Timing for the Slave Parallel Configuration Mode (Continued)
All Speed Grades
Symbol
Hold Times
TSMCCD
Description
Min
Max
Units
The time from the rising transition at the CCLK pin to the point when data is
last held at the D0-D7 pins
0
0
0
-
-
-
ns
ns
ns
TSMCCCS
TSMWCC
The time from the rising transition at the CCLK pin to the point when a logic
level is last held at the CS_B pin
The time from the rising transition at the CCLK pin to the point when a logic
level is last held at the RDWR_B pin
Clock Timing
TCCH
The High pulse width at the CCLK input pin
The Low pulse width at the CCLK input pin
5
5
-
-
ns
TCCL
-
ns
FCCPAR
Frequency of the clock
signal at the CCLK input
pin
No bitstream
compression
Not using the BUSY pin(2)
Using the BUSY pin
50
66
20
MHz
MHz
MHz
-
With bitstream compression
-
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 4.
2. In the Slave Parallel mode, it is necessary to use the BUSY pin when the CCLK frequency exceeds this maximum specification.
3. Some Xilinx documents may refer to Parallel modes as "SelectMAP" modes.
16
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DS312-3 (v1.0) March 1, 2005
Advance Product Specification
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