R
Spartan-3 1.2V FPGA Family: Functional Description
Configuration is automatically initiated after power-on
unless it is delayed by the user. INIT_B is an open-drain line
that the FPGA holds Low during the clearing of the configu-
ration memory. Extending the time that the pin is Low
causes the configuration sequencer to wait. Thus, configu-
ration is delayed by preventing entry into the phase where
data is loaded.
The default start-up sequence, shown in Figure 25, serves
as a transition to the User mode. The default start-up
sequence is that one CCLK cycle after DONE goes High,
the Global Three-State signal (GTS) is released. This per-
mits device outputs to which signals have been assigned to
become active. One CCLK cycle later, the Global Write
Enable (GWE) signal is released. This permits the internal
storage elements to begin changing state in response to the
design logic and the user clock.
The configuration process can also be initiated by asserting
the PROG_B pin. The end of the memory-clearing phase is
signaled by the INIT_B pin going High. At this point, the con-
figuration data is written to the FPGA. The FPGA holds the
Global Set/Reset (GSR) signal active throughout configura-
tion, keeping all flip-flops on the device in a reset state. The
completion of the entire process is signaled by the DONE
pin going High.
The relative timing of configuration events can be changed
via the BitGen options in the Xilinx development software. In
addition, the GTS and GWE events can be made depen-
dent on the DONE pins of multiple devices all going High,
forcing the devices to start synchronously. The sequence
can also be paused at any stage, until lock has been
achieved on any DCM.
Default Cycles
Readback
Start-Up Clock
Using Slave Parallel mode, configuration data from the
FPGA can be read back. Readback is supported only in the
Slave Parallel and Boundary-Scan modes.
Phase
0
1
2
3
4
5
6 7
Along with the configuration data, it is possible to read back
the contents of all registers, distributed SelectRAM, and
block RAM resources. This capability is used for real-time
debugging.
DONE
GTS
GSR
GWE
Sync-to-DONE
Start-Up Clock
Phase
0
1
2
3
4
5
6 7
DONE High
DONE
GTS
GSR
GWE
DS099_028_040803
Notes:
1. The BitGen option StartupClk in the Xilinx
development software selects the CCLK input,
TCK input, or a user-designated global clock input
(the GCLK0 - GCLK7 pins) for receiving the clock
signal that synchronizes Start-Up.
Figure 25: Default Start-Up Sequence
DS099-2 (v1.2) July 11, 2003
Advance Product Specification
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