R
Spartan-3 1.2V FPGA Family: Functional Description
Set PROG_B Low
after Power-On
Power-On
VCCINT >1V
and VCCAUX > 2V
No
and VCCO Bank 4 > 1V
Yes
Clear
configuration
memory
Yes
PROG_B = Low
No
No
INIT_B = High?
Yes
Sample
mode pins
(JTAG port becomes
available)
Load
JShutdown
instruction
Shutdown
sequence
Load CFG_IN
instruction
Load configuration
data frames
No
CRC
correct?
INIT_B goes Low.
Abort Start-Up
Yes
Synchronous
TAP reset
(Clock five 1's
on TMS)
Load JSTART
instruction
Start-Up
sequence
User mode
Yes
No
Reconfigure?
DS099_27_041103
Figure 24: Boundary-Scan Configuration Flow Diagram
38
40
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DS099-2 (v1.2) July 11, 2003
Advance Product Specification
XILINX [ XILINX, INC ]
