— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
R
Virtex-II Platform FPGAs: Functional Description
3. “NO_CHANGE”
Initial memory content is determined by the INIT_xx attri-
butes. Separate attributes determine the output register
value after device configuration (INIT) and SSR is asserted
(SRVAL). Both attributes (INIT_B and SRVAL) are available
for each port when a block SelectRAM resource is config-
ured as dual-port RAM.
The “NO_CHANGE” option maintains the content of the
output registers, regardless of the write operation. The
clock edge during the write mode has no effect on the
content of the data output register DO. When the port is
configured as “NO_CHANGE”, only a read operation
loads a new value in the output register DO, as shown in
Figure 33.
Locations
Virtex-II SelectRAM memory blocks are located in either
four or six columns. The number of blocks per column
depends of the device array size and is equivalent to the
number of CLBs in a column divided by four. Column loca-
tions are shown in Table 18.
Internal
Memory
DO
Data_in
No change during write
DI
Table 18: SelectRAM Memory Floor Plan
CLK
WE
SelectRAM Blocks
Device
Columns
Per Column
Total
4
Data_in
Address
New
XC2V40
2
2
4
4
4
4
4
6
6
6
6
2
aa
XC2V80
4
8
XC2V250
XC2V500
XC2V1000
XC2V1500
XC2V2000
XC2V3000
XC2V4000
XC2V6000
XC2V8000
6
24
RAM Contents
Data_out
Old
New
8
32
Last Read Cycle Content (no change)
10
12
14
16
20
24
28
40
DS031_12_102000
48
Figure 33: NO_CHANGE Mode
56
Control Pins and Attributes
96
Virtex-II SelectRAM memory has two independent ports
with the control signals described in Table 17. All control
inputs including the clock have an optional inversion.
120
144
168
Table 17: Control Functions
Control Signal
Function
CLK
EN
Read and Write Clock
Enable affects Read, Write, Set, Reset
Write Enable
WE
SSR
Set DO register to SRVAL (attribute)
DS031-2 (v4.0) April 7, 2014
Product Specification
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