R
Spartan-IIE FPGA Family: Pinout Tables
Additional FG456 Package Pins (Continued)
VCCO Bank 1 Pins
F15
F16
H17
P16
T14
T10
P7
G13
J16
R17
U15
U7
G14
K16
T17
U16
U8
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
VCCO Bank 2 Pins
G17
VCCO Bank 3 Pins
N16
VCCO Bank 4 Pins
T13
VCCO Bank 5 Pins
T9
VCCO Bank 6 Pins
N7
R6
T6
VCCO Bank 7 Pins
G6
GND Pins
A1
H6
J7
K7
A2(2)
J9
A22
J10
B1(2)
J11
B2
J12
B21
J13
L9
C3
J14
C20
K9
G11
K10
L12
M13
P9
G12
K11
K12
L14
M16
P11
AA2
K13
L16
K14
M7
L7
L10
L11
M12
N14
Y20
-
L13
M9
M10
N12
T11
AB1
M11
N13
T12
AB22
M14
N9
N10
P13
AA21
N11
P14
AA22(2)
P10
Y4(2)
P12
AA4(2)
Y3
-
Not Connected Pins
A2(2) B1(2)
Notes:
D4(1)
D19(1)
W4(1)
W19(1)
Y4(2)
AA4(2)
AA22(2)
1. VCCINT connections in XC2S400E and XC2S600E. No Connects (no internal connection) in XC2S100E, XC2S150E, XC2S200E,
and XC2S300E.
2. GND connections in XC2S400E and XC2S600E. No Connects (no internal connection) in XC2S100E, XC2S150E, XC2S200E, and
XC2S300E
FG676 Pinouts (XC2S400E, XC2S600E)
Pad Name
Device-Specific Pinouts
LVDS Async.
VREF
Function
Bank
Pin
B1
D3
C2
C1
D2
D1
E2
E1
Output Option
Option
XC2S400E
XC2S600E
TMS
TMS
I/O
-
-
-
-
-
-
-
-
-
-
TMS
7
7
7
7
7
7
7
-
I/O
I/O
I/O, L204P
-
-
I/O, L204P
I/O, L204N
I/O, L203P_Y
I/O, L203N_Y
I/O, L202P_YY
I/O, L202N_YY
I/O, L204N
-
-
I/O, L203P
XC2S600E
XC2S600E
All
-
I/O, L203N
I/O
I/O, L202P_YY
I/O, L202N_YY
I/O, L202P_YY
I/O, L202N_YY
All
DS077-4 (2.3) June 18, 2008
www.xilinx.com
89
Product Specification
XILINX [ XILINX, INC ]
