R
Spartan-IIE FPGA Family: Pinout Tables
FG456 Pinouts (XC2S100E, XC2S150E, XC2S200E, XC2S300E, XC2S400E, XC2S600E)
Pad Name
LVDS
Async.
Output
Option
Device-Specific Pinouts: XC2S
VREF
Option
Function Bank Pin
100E
150E
200E
300E
400E
600E
I/O,
0
A6
All
-
I/O,
I/O,
I/O,
I/O,
I/O,
I/O,
L#P_YY
L2P_YY
L3P_YY
L3P_YY
L3P_YY
L3P_YY
L3P_YY
I/O, VREF
Bank 0,
L#N_YY
0
B6
All
All
I/O, VREF I/O, VREF I/O, VREF I/O, VREF
I/O, VREF
Bank 0,
L3N_YY
I/O, VREF
Bank 0,
L3N_YY
Bank 0,
L2N_YY
Bank 0,
L3N_YY
Bank 0,
L3N_YY
Bank 0,
L3N_YY
I/O
0
0
0
0
0
C6
A5
B5
D6
B4
XC2S100E
-
-
-
-
-
I/O, L1P_Y
I/O
I/O, L2P
I/O, L2N
-
I/O
I/O, L2P
I/O, L2N
-
I/O
I/O
I/O
I/O, L#P
I/O, L#N
I/O
XC2S100E
I/O, L1N_Y
I/O, L2P
I/O, L2N
I/O
I/O, L2P
I/O, L2N
I/O
I/O, L2P
I/O, L2N
I/O
-
-
-
-
I/O, L#P
XC2S100E,
200E, 300E,
400E, 600E
I/O, L0P_Y
I/O, L1P
I/O, L1P_Y I/O, L1P_Y I/O, L1P_Y I/O, L1P_Y
I/O, L#N
0
C5
XC2S100E, XC2S200E, I/O, L0N_Y
200E, 300E, 300E,
400E, 600E 400E, 600E
I/O, L1N
I/O, VREF I/O, VREF
I/O, VREF
Bank 0,
L1N_Y
I/O, VREF
Bank 0,
L1N_Y
Bank 0,
L1N_Y
Bank 0,
L1N_Y
I/O
0
0
A4
A3
-
-
-
I/O
-
I/O
I/O
I/O
I/O
I/O
I/O, L#P
XC2S150E,
400E, 600E
I/O, L0P_Y
I/O, L0P
I/O, L0P
I/O, L0P_Y I/O, L0P_Y
I/O, L#N
0
B3
XC2S150E,
400E, 600E
-
-
I/O, L0N_Y
I/O, L0N
I/O, L0N
I/O, L0N_Y I/O, L0N_Y
I/O
0
0
-
C4
D5
E6
-
-
-
-
-
-
-
-
-
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TCK
TCK
TCK
TCK
TCK
TCK
TCK
Notes:
1. Although designated with the _YY suffix in the XC2S100E, XC2S150E, XC2S200E, and XC2S300E, these differential pairs are not
asynchronous in the XC2S400E.
FG456 Differential Clock Pins
P
N
Clock
GCK0
GCK1
GCK2
GCK3
Bank
Pin
AA12
AB12
A11
Name
Pin
Y12
Name
4
5
1
0
GCK0, I
GCK1, I
GCK2, I
GCK3, I
I/O (DLL), L#P
I/O (DLL), L#N
I/O (DLL), L#P
I/O (DLL), L#N
AB11
A12
C11
B11
Additional FG456 Package Pins
VCCINT Pins
D4(1)
G16
U6
D19(1)
H7
E5
H16
V5
E18
F6
F17
T7
W19(1)
G7
T8
-
G8
T15
-
G15
R7
R16
W4(1)
T16
-
U17
V18
VCCO Bank 0 Pins
F7
F8
G9
G10
-
-
-
-
-
88
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DS077-4 (2.3) June 18, 2008
Product Specification
XILINX [ XILINX, INC ]
