50
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Spartan-II FPGA Family:
Functional Description
Product Specification
memory elements for easy and quick routing of signals on
and off the chip.
Values stored in static memory cells control all the
configurable logic elements and interconnect resources.
These values load into the memory cells on power-up, and
can reload if necessary to change the function of the device.
Each of these elements will be discussed in detail in the
following sections.
DS001-2 (v2.8) June 13, 2008
Architectural Description
Spartan-II FPGA Array
The Spartan
®
-II field-programmable gate array, shown in
Figure 2,
is composed of five major configurable elements:
•
•
•
•
•
IOBs provide the interface between the package pins
and the internal logic
CLBs provide the functional elements for constructing
most logic
Dedicated block RAM memories of 4096 bits each
Clock DLLs for clock-distribution delay compensation
and clock domain control
Versatile multi-level interconnect structure
Input/Output Block
The Spartan-II FPGA IOB, as seen in
Figure 2,
features
inputs and outputs that support a wide variety of I/O
signaling standards. These high-speed inputs and outputs
are capable of supporting various state of the art memory
and bus interfaces.
Table 3
lists several of the standards
which are supported along with the required reference,
output and termination voltages needed to meet the
standard.
As can be seen in
Figure 2,
the CLBs form the central logic
structure with easy access to all support and routing
structures. The IOBs are located around all the logic and
T
SR
D
Q
V
CCO
Package
Pin
VCC
OE
TFF
CLK
TCE
SR
SR
O
D
Q
CK
EC
Programmable
Bias &
ESD Network
I/O
Package Pin
OFF
CK
OCE
EC
Programmable
Output Buffer
Internal
Reference
IQ
SR
I
D
Q
Programmable
Delay
Programmable
Input Buffer
I/O, V
REF
Package Pin
IFF
CK
ICE
EC
To Next I/O
To Other
External V
REF
Inputs
of Bank
DS001_02_090600
Figure 2:
Spartan-II FPGA Input/Output Block (IOB)
© 2000-2008 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, the Brand Window, and other designated brands included herein are trademarks of Xilinx, Inc. All other
trademarks are the property of their respective owners.
DS001-2 (v2.8) June 13, 2008
Product Specification
Module 2 of 4
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