R
Spartan-II FPGA Family: Functional Description
COUT
YB
Y
G4
G3
G2
G1
I4
Look-Up
I3 Table
O
I2
I1
D
Carry
and
Control
Logic
CK
EC
R
S
Q
YQ
F5IN
BY
SR
XB
X
F4
F3
F2
F1
I4
S
D
Carry
and
Control
Logic
CK
EC
R
Q
XQ
Look-Up
I3 Table
O
I2
I1
BX
CIN
CLK
CE
DS001_04_091400
Figure 4:
Spartan-II CLB Slice
(two identical slices in each CLB)
Storage Elements
Storage elements in the Spartan-II FPGA slice can be
configured either as edge-triggered D-type flip-flops or as
level-sensitive latches. The D inputs can be driven either by
function generators within the slice or directly from slice
inputs, bypassing the function generators.
In addition to Clock and Clock Enable signals, each slice
has synchronous set and reset signals (SR and BY). SR
forces a storage element into the initialization state
specified for it in the configuration. BY forces it into the
DS001-2 (v2.8) June 13, 2008
Product Specification
opposite state. Alternatively, these signals may be
configured to operate asynchronously.
All control signals are independently invertible, and are
shared by the two flip-flops within the slice.
Additional Logic
The F5 multiplexer in each slice combines the function
generator outputs. This combination provides either a
function generator that can implement any 5-input function,
a 4:1 multiplexer, or selected functions of up to nine inputs.
Module 2 of 4
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