R
XC18V00 Series In-System-Programmable Configuration PROMs
Pinout and Pin Description
provides a list of the pin names and descriptions for the 44-pin VQFP and PLCC and the 20-pin SOIC and PLCC
packages.
Table 1:
Pin Names and Descriptions
Pin
Name
D0
Boundary-
Scan Order
4
3
Function
DATA OUT
OUTPUT
ENABLE
DATA OUT
OUTPUT
ENABLE
DATA OUT
OUTPUT
ENABLE
DATA OUT
OUTPUT
ENABLE
DATA OUT
OUTPUT
ENABLE
DATA OUT
OUTPUT
ENABLE
DATA OUT
OUTPUT
ENABLE
DATA OUT
OUTPUT
ENABLE
DATA IN
Pin Description
D0 is the DATA output pin to provide data for
configuring an FPGA in serial mode.
44-pin VQFP
40
44-pin
PLCC
2
20-pin
SOIC &
PLCC
1
D1
6
5
D2
2
1
D0-D7 are the output pins to provide parallel
data for configuring a Xilinx FPGA in Slave
Parallel/SelectMAP mode.
D1-D7 remain in high-Z state when the PROM
operates in serial mode.
D1-D7 can be left unconnected when the
PROM is used in serial mode.
29
35
16
42
4
2
D3
8
7
27
33
15
D4
24
23
9
15
7
(1)
D5
10
9
25
31
14
D6
17
16
14
20
9
D7
14
13
19
25
12
CLK
0
Each rising edge on the CLK input increments
the internal address counter if both CE is Low
and OE/RESET is High.
When Low, this input holds the address
counter reset and the DATA output is in a high-
Z state. This is a bidirectional open-drain pin
that is held Low while the PROM is reset.
Polarity is NOT programmable.
When CE is High, the device is put into low-
power standby mode, the address counter is
reset, and the DATA pins are put in a high-Z
state.
Allows JTAG CONFIG instruction to initiate
FPGA configuration without powering down
FPGA. This is an open-drain output that is
pulsed Low by the JTAG CONFIG command.
43
5
3
OE/
RESET
20
19
18
DATA IN
DATA OUT
OUTPUT
ENABLE
DATA IN
13
19
8
CE
15
15
21
10
CF
22
21
DATA OUT
OUTPUT
ENABLE
10
16
7
(1)
DS026 (v5.2) January 11, 2008
Product Specification
2
XILINX [ XILINX, INC ]
