Asynchronous FIFO V1.0.3
Signal
Description
Direction
Output ReaD_COUNT: count vector
(unsigned binary) of number
of data word currently in
FIFO, synchronized to
RD_CLK. If (2^R+1)<(FIFO
depth+1), the least signifi-
cant bits of count are truncat-
ed (R=0, produces a half full
flag)
Output ReaD_ACKnowledge: hand-
shake signal RD_EN active
on prior RD_CLK edge has
placed next data word on Q
output pins
Output ReadD_ERRor: handshake
signal RD_EN active on prior
RD_CLK edge was ignored
and subsequently data on Q
output pins was not updated
•
Data Count:
Two Data Counts, one for each clock
domain may be enabled by selecting the appropriate
radio button. Once selected the corresponding count
width dialog box becomes active.Valid count widths are
any integer from 1 to N (where 2^N = (FIFO Depth + 1).
If an integer greater than N is entered in will turn red
and core generation will be inhibited until this error is
corrected. The default value is 2 (encoded quadrant
flags).
•
Create RPM:
When this box is checked the module will
be generated will relative location attributes attached.
The FIFO with be produced with two (or three if
distributed memory was selected) individual RPMs. A
single RPM is not produced to allow an RPM’d FIFO to
support varying footprints.
Signal
RD_
COUNT [R:0]
RD_ACK
RD_ERR
Parameter Values in XCO File
Names of XCO file parameters and their parameter values
are identical to the names and values shown in the GUI,
except that underscore characters (_) are used instead of
spaces The text in an XCO file is case insensitive.
Table 3 shows the XCO file parameters and values, as well
as summarizing the GUI defaults. The following is an exam-
ple of the CSET parameters in an XCO file:
CSET component_name = my_fifo_name
CSET fifo_depth = 255
CSET input_data_width = 8
CSET memory_type = block
CSET almost_full_flag = TRUE
CSET almost_empty_flag = TRUE
CSET write_count = TRUE
CSET write_count_width = 1
CSET read_count = TRUE
CSET read_count_width = 8
CSET write_acknowledge = TRUE
CSET write_acknowledge_sense = active_high
CSET write_error = TRUE
CSET write_error_sense = active_low
CSET read_acknowledge = TRUE
CSET read_acknowledge_sense = active_high
CSET read_error = TRUE
CSET read_error_sense = active_low
CSET create_rpm = TRUE
•
•
•
•
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Memory Type:
Select the appropriate radio button for
the type of memory desired. Block Memory implements
the FIFO’s memory using SelectRAM+. Selecting the
Distributed Memory radio button will implement FIFO
memory using LUT based dual port memory. The
defaults is Block Memory.
Input Data Width:
Enter the width of the input data bus
(also the width of the output data bus). The valid range
is 1 - 64. The default value is 16.
FIFO Depth: Select
the available depth from the pull
down list. Note: the available depths are dependent on
the selected memory type. Since one memory location
has been sacrificed in the interest of optimizing FIFO
performance available, depths are (2^N –1). When
using SelectRAM+, N may be any integer from 1 to 12,
with additional restrictions based on the Data Width.
Distributed RAM FIFOs have a maximum depth of 255
(N = 8) and Block Memory FIFO have a maximum
depth of 4095.
Optional Flags:
Generate Almost Full and Almost
Empty status flags by selecting the appropriate check
boxes. The default value is unchecked.
Optional Handshake Signals:
Handshaking control
signals (acknowledge and/or error) can be enabled via
the Handshaking Options button. A pop up dialog box
will appear, as shown in Figure 2. Each of the four
handshake signals (write acknowledge, write error, read
acknowledge, and read error) can be enabled by
selecting the appropriate check box. Selecting any
handshaking signal will enable its associated Active
High, Active Low radio buttons (default is Active High).
To make any of these flags Active Low, check the
corresponding Active Low check box. The default state
for all four handshaking signals is disabled.
Core Resource Utilization
The resource requirements of the asynchronous FIFO are
highly dependent on the memory size, memory type and
the presence of optional ports. Resource utilization can be
estimated by addition of the requirements for the FIFOs
memory and control logic. Table 3 lists the number of
SelectRAM+ blocks required to implement various width
and depth combinations when using SelectRAM+ blocks
for the FIFO’s memory.
4
December 17, 1999
XILINX [ XILINX, INC ]
