Asynchronous FIFO V1.0.3
December 17, 1999
Product Specification
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Xilinx Inc.
2100 Logic Drive
San Jose, CA 95124
Phone: +1 408-559-7778
Fax:
+1 408-559-7114
E-mail: coregen@xilinx.com
URL:
www.xilinx.com/support/techsup/appinfo
www.xilinx.com/ipcenter
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Features
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Drop-in module for Virtex, Virtex
TM
-E, and Spartan
TM
-II
FPGAs
Supports data widths up to 64 bits
Supports memory depths of up to 4095 locations
Memory may be implemented in either SelectRAM+ or
Distributed RAM
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Fully synchronous and independent clock domains for
the read and write ports
Supports full and empty status flags
Optional almost_full and almost_empty status flags
Invalid read or write requests are rejected without
affecting the FIFO state
Four optional handshake signals (wr_ack, wr_err,
rd_ack, rd_err) provide feedback (acknowledgment or
rejection) in response to write and read requests in the
prior clock cycle
Optional count vector(s) provides visibility into number
of data words currently in the FIFO, synchronized to
either clock domain
Incorporates Xilinx Smart-IP technology for maximum
performance
To be used with version 2.1i or later of the Xilinx CORE
Generator System
Functional Description
The Asynchronous FIFO is a First In First Out memory
queue. Its control logic performs all the necessary read and
write pointer management, generates status flags, and
optional handshake signals for interfacing to user logic. The
individual read and write ports are fully synchronous (all
operations qualified by a rising clock edge), but this FIFO
Figure 1: Asynchronous FIFO Parameterization
Screen
Figure 2: Handshaking Options Dialog Box
December 17, 1999
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XILINX [ XILINX, INC ]
