XC9500XV Family High-Performance CPLD
R
Macrocell
Each XC9500XV macrocell may be individually configured
for a combinatorial or registered function. The macrocell
and associated FB logic is shown in
Figure 3.
Five direct product terms from the AND-array are available
for use as primary data inputs (to the OR and XOR gates) to
implement combinatorial functions, or as control inputs
including clock, clock enable, set/reset, and output enable.
The product term allocator associated with each macrocell
selects how the five direct terms are used.
The macrocell register can be configured as a D-type or
T-type flip-flop, or it may be bypassed for combinatorial
operation. Each register supports both asynchronous set
and reset operations. During power-up, all user registers
are initialized to the user-defined preload state (default to 0
if unspecified).
54
Global
Set/Reset
Global
Clocks
3
Additional
Product
Terms
(from other
macrocells)
Product Term Set
1
0
S
D/T Q
To
FastCONNECTII
Switch Matrix
Product
Term
Allocator
EC
Product Term Clock Enable
Product Term Clock
Product Term Reset
OUT
Product Term OE
PTOE
To
I/O Blocks
R
Additional
Product
Terms
(from other
macrocells)
DS049_03_041400
Figure 3:
XC9500XV Macrocell Within Function Block
Note: See
Figure 8
for additional clock enable details
4
1-800-255-7778
DS049 (v2.0) January 15, 2001
Advance Product Specification
XILINX [ XILINX, INC ]
