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XC9500XV Family High-Performance
CPLD
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DS049 (v2.0) January 15, 2001
Advance Product Specification
Features
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Optimized for high-performance 2.5V systems
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3.5 ns pin-to-pin logic delays
Small footprint packages including VQFPs, TQFPs
and CSPs (Chip Scale Package)
Lower power operation
Multi-voltage operation
FastFLASH technology
In-system programmable
Output banking (XC95144XV, XC95288XV)
Superior pin-locking and routability with
FastCONNECT II™ switch matrix
Extra wide 54-input Function Blocks
Up to 90 product-terms per macrocell with
individual product-term allocation
Local clock inversion with three global and one
product-term clocks
Individual output enable per output pin with local
inversion
Input hysteresis on all user and boundary-scan pin
inputs
Bus-hold circuitry on all user pin inputs
Full IEEE Standard 1149.1 boundary-scan (JTAG)
support on all devices
36 to 288 macrocells, with 800 to 6400 usable
gates
Family Overview
The XC9500XV family is a 2.5V CPLD family targeted for
high-performance, low-voltage applications in leading-edge
communications and computing systems, where high
device reliability and low power dissipation is important.
Each XC9500XV device supports in-system programming
(ISP) and the full IEEE 1149.1 (JTAG) boundary-scan,
allowing superior debug and design iteration capability for
small form-factor packages. The XC9500XV family is
designed to work closely with the Xilinx Spartan-XL and Vir-
tex FPGA families, allowing system designers to partition
logic optimally between fast interface circuitry and high-den-
sity general purpose logic. As shown in
Table 1,
logic den-
sity of the XC9500XV devices ranges from 800 to 6400
usable gates with 36 to 288 registers, respectively. Multiple
package options and associated I/O capacity are shown in
Table 2.
The XC9500XV family members are fully pin-com-
patible, allowing easy design migration across multiple den-
sity options in a given package footprint.
The XC9500XV architectural features address the require-
ments of in-system programmability. Enhanced pin-locking
capability avoids costly board rework. In-system program-
ming throughout the full commercial operating range and a
high programming endurance rating provide worry-free
reconfigurations of system field upgrades. Extended data
retention supports longer and more reliable system operat-
ing life.
Advanced system features include output slew rate control
and user-programmable ground pins to help reduce system
noise. Each user pin is compatible with 3.3V, 2.5V, and 1.8V
inputs, and the outputs may be configured for 3.3V, 2.5V, or
1.8V operation. The XC9500XV device exhibits symmetric
full 2.5V output voltage swing to allow balanced rise and fall
times.
Advanced system features
Four pin-compatible device densities
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Fast concurrent programming
Slew rate control on individual outputs
Enhanced data security features
Excellent quality and reliability
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10,000 program/erase cycles endurance rating
20 year data retention
Architecture Description
Each XC9500XV device is a subsystem consisting of multi-
ple Function Blocks (FBs) and I/O Blocks (IOBs) fully inter-
connected by the FastCONNECT II switch matrix. The IOB
provides buffering for device inputs and outputs. Each FB
provides programmable logic capability with extra wide 54
inputs and 18 outputs. The FastCONNECT II switch matrix
connects all FB outputs and input signals to the FB inputs.
For each FB, up to 18 outputs (depending on package
pin-count) and associated output enable signals drive
directly to the IOBs. See
Figure 1.
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Pin-compatible with 3.3V core XC9500XL family in
common package footprints
Hot Plugging capability
© 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS049 (v2.0) January 15, 2001
Advance Product Specification
1-800-255-7778
1
XILINX [ XILINX, INC ]
