R
MultiPRO Desktop Tool
lists some third-party sources for mating connectors for 2 mm pitch, 14-conductor ribbon cable.
Table 3:
Mating Connectors for 2 mm pitch, 14 Conductor Ribbon Cable
Manufacturer
Comm Con
OUPIIN
Notes:
1.
2.
3.
Also available in surface mount or without keyed shroud.
Some manufacturer’s pin assignments do not conform to Xilinx pin assignments.
Please refer to the manufacturer's data sheet for more information.
Additional 14-pin ribbon cables can be purchased separately from the
Part Number
2422-14G2
3112-14G00SBA/SN
Table 4
lists third-party sources for mating connectors for 2 mm pitch, 34-conductor ribbon cable.
Table 4:
Mating Connectors for 2 mm pitch, 34 Conductor Ribbon Cable
Manufacturer
Comm Con
OUPIIN
Part Number
2422-34G2
3112-34G00SBA/SN
Notes:
Also available in surface mount or without keyed shroud.
Interface Pin Descriptions
The interface pins for the Serial/JTAG/SPI, SelectMAP, and adapter ports are described in
and
Table 7,
respectively.
Table 5:
SS/JTAG/SPI Port: 14-Pin Ribbon Cable Connector
Ribbon
Cable
Number
2
Slave-Serial
JTAG
SPI
(2)
Configuration Configuration Programming
Mode
Mode
Mode
V
REF
V
REF
V
REF
Type
In
Description
Target Reference Voltage.
(3)
This pin should be connected to a
voltage bus on the target system that serves the JTAG, slave-serial
interface. or SPI. For example, when programming a Coolrunner-II
device using the JTAG port, V
REF
should be connected to the target
V
AUX
bus.
Configuration Reset.
This pin is used to force a reconfiguration of
the target FPGA(s). It should be connected to the PROG_B pin of the
target FPGA for a single-device system, or to the PROG_B pin of all
FPGAs in parallel in a daisy-chain configuration.
Configuration Clock.
FPGAs load one configuration bit per CCLK
cycle in slave-serial mode. CCLK should be connected to the CCLK
pin on the target FPGA for a single-device configuration, or to the
CCLK pin of all FPGAs in parallel in a daisy-chain configuration.
Configuration Done.
This pin indicates to MultiPRO tool that target
FPGAs have received the entire configuration bitstream. It should be
connected to the Done pin on all FPGAs in parallel for daisy-chained
configurations. Additional CCLK cycles are issued following the positive
transition of Done to insure that the configuration process is complete.
Configuration Data Input.
This is the serial input data stream for
target FPGAs. It should be connected to the DIN pin of the target
FPGA in a single-device system, or to the DIN pin of the first FPGA
in a daisy-chain configuration.
Test Driver.
This pin is reserved for Xilinx diagnostics and should not
be connected to any target circuitry.
memory is being cleared. It should be connected to the INIT_B pin of
the target FPGA for a single-device system, or to the INIT_B pin on
all FPGAs in parallel in a daisy-chain configuration.
4
PROG
–
–
Out
6
CCLK
–
–
Out
8
DONE
–
–
In
10
DIN
–
–
Out
12
14
N/C
INIT
N/C
N/C
N/C
N/C
Out
BIDIR
Configuration Initialize.
This pin indicates that configuration
DS114 (v1.9) February 8, 2008
Product Specification
7
XILINX [ XILINX, INC ]
