R
XA Spartan-3A DSP Automotive FPGA Family Data Sheet
Single-Ended I/O Standards
Table 11: Recommended Operating Conditions for User I/Os Using Single-Ended Standards
VCCO for Drivers(2)
VREF
VIL
Max (V)
0.8
VIH
Min (V)
IOSTANDARD
Attribute
Min (V) Max (V)
Nom (V)
3.3
3.3
2.5
1.8
1.5
1.2
3.3
1.5
1.5
1.8
1.8
1.8
1.8
1.8
2.5
2.5
3.3
3.3
Min (V)
Nom (V)
Max (V)
LVTTL
3.0
3.0
2.3
1.65
1.4
1.1
3.0
1.4
1.4
1.7
1.7
1.7
1.7
1.7
2.3
2.3
3.0
3.0
3.6
3.6
2.7
1.95
1.6
1.3
3.6
1.6
1.6
1.9
1.9
1.9
1.9
1.9
2.7
2.7
3.6
3.6
2.0
LVCMOS33(4)
LVCMOS25(4,5)
LVCMOS18(4)
LVCMOS15(4)
LVCMOS12(4)
PCI33_3(6)
HSTL_I
0.8
2.0
0.7
1.7
VREF is not used for
these I/O standards
0.4
0.8
0.4
0.8
0.4
0.7
0.3 • VCCO
VREF - 0.1
VREF - 0.1
0.5 • VCCO
VREF + 0.1
VREF + 0.1
VREF + 0.1
VREF + 0.1
VREF + 0.1
VREF + 0.125
VREF + 0.125
VREF + 0.150
VREF + 0.150
VREF + 0.2
VREF + 0.2
0.68
-
0.75
0.9
0.9
-
HSTL_III
HSTL_I_18
HSTL_II_18
HSTL_III_18
SSTL18_I
0.8
-
0.9
1.1
-
VREF - 0.1
0.9
VREF - 0.1
VREF - 0.1
-
1.1
-
0.833
0.833
1.15
1.15
1.3
1.3
0.900
0.900
1.25
1.25
1.5
0.969
0.969
1.38
1.38
1.7
1.7
V
REF - 0.125
SSTL18_II
SSTL2_I
VREF - 0.125
V
REF - 0.150
REF - 0.150
SSTL2_II
V
SSTL3_I
VREF - 0.2
VREF - 0.2
SSTL3_II
1.5
Notes:
1. Descriptions of the symbols used in this table are as follows:
V
V
V
V
– the supply voltage for output drivers
– the reference voltage for setting the input switching threshold
– the input voltage that indicates a Low logic level
– the input voltage that indicates a High logic level
CCO
REF
IL
IH
2. In general, the V
rails supply only output drivers, not input circuits. The exceptions are for LVCMOS25 inputs when V
= 3.3V range
CCO
CCAUX
and for PCI I/O standards.
3. For device operation, the maximum signal voltage (V max) can be as high as V max. See Table 4.
IH
IN
4. There is approximately 100 mV of hysteresis on inputs using LVCMOS33 and LVCMOS25 I/O standards.
5. All Dedicated pins (PROG_B, DONE, SUSPEND, TCK, TDI, TDO, and TMS) draw power from the V
rail and use the LVCMOS25 or
CCAUX
LVCMOS33 standard depending on V
When using these pins as part of a standard 2.5V configuration interface, apply 2.5V to the V
well as throughout configuration.
. The Dual-Purpose configuration pins use the LVCMOS25 standard before the User mode.
CCAUX
lines of Banks 0, 1, and 2 at power-on as
CCO
6. For information on PCI IP solutions, see www.xilinx.com/pci. The PCI IOSTANDARD is not supported on input-only pins.
DS705 (v1.1) January 20, 2009
www.xilinx.com
Product Specification
11
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