R
Pinout Descriptions
Table 152: FG400 Package Pinout (Continued)
Table 152: FG400 Package Pinout (Continued)
XC3S1200E
XC3S1600E
Pin Name
XC3S1200E
XC3S1600E
Pin Name
FG400
Ball
FG400
Ball
Bank
Type
Bank
Type
VCCAUX TMS
E17
D11
H12
J7
JTAG
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
J12
K9
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
K11
L10
L12
M9
K4
L17
M14
N9
M11
M13
N8
U10
H9
N10
N12
H11
H13
J8
J10
User I/Os by Bank
Table 153 indicates how the 304 available user-I/O pins are
distributed between the four I/O banks on the FG400 pack-
age.
Table 153: User I/Os Per Bank for the XC3S1200E and XC3S1600E in the FG400 Package
All Possible I/O Pins by Type
Package
Edge
Maximum
I/O
(1)
(1)
I/O Bank
I/O
43
INPUT
20
DUAL
1
VREF
CLK
Top
0
1
2
3
78
74
6
6
8
(2)
Right
35
12
21
24
0
0
(2)
Bottom
Left
78
30
18
6
0
74
48
12
6
8
TOTAL
304
156
62
46
24
16
Notes:
1. Some VREF and CLK pins are on INPUT pins.
2. The eight global clock pins in this bank have optional functionality during configuration and are counted in the DUAL column.
Footprint Migration Differences
The XC3S1200E and XC3S1600E FPGAs have identical
footprints in the FG400 package. Designs can migrate
between the XC3S1200E and XC3S1600E FPGAs without
further consideration.
DS312-4 (v3.8) August 26, 2009
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Product Specification
XILINX [ XILINX, INC ]
