R
Spartan-II FPGA Family: Functional Description
3-State
Lines
CLB
CLB
CLB
CLB
DS001_07_090600
Figure 7: BUFT Connections to Dedicated Horizontal Bus Lines
networks. The DLL monitors the input clock and the
Clock Distribution
distributed clock, and automatically adjusts a clock delay
element. Additional delay is introduced such that clock
edges reach internal flip-flops exactly one clock period after
they arrive at the input. This closed-loop system effectively
eliminates clock-distribution delay by ensuring that clock
edges arrive at internal flip-flops in synchronism with clock
edges arriving at the input.
The Spartan-II family provides high-speed, low-skew clock
distribution through the primary global routing resources
described above. A typical clock distribution net is shown in
Figure 8.
Four global buffers are provided, two at the top center of the
device and two at the bottom center. These drive the four
primary global nets that in turn drive any clock pin.
In addition to eliminating clock-distribution delay, the DLL
provides advanced control of multiple clock domains. The
DLL provides four quadrature phases of the source clock,
can double the clock, or divide the clock by 1.5, 2, 2.5, 3, 4,
5, 8, or 16. It has six outputs.
Four dedicated clock pads are provided, one adjacent to
each of the global buffers. The input to the global buffer is
selected either from these pads or from signals in the
general purpose routing. Global clock pins do not have the
option for internal, weak pull-up resistors.
The DLL also operates as a clock mirror. By driving the
output from a DLL off-chip and then back on again, the DLL
can be used to deskew a board level clock among multiple
Spartan-II devices.
GCLKPAD2
GCLKBUF2
GCLKPAD3
GCLKBUF3
Global
Clock Rows
Global Clock
Column
In order to guarantee that the system clock is operating
correctly prior to the FPGA starting up after configuration,
the DLL can delay the completion of the configuration
process until after it has achieved lock.
Boundary Scan
Global Clock
Spine
Spartan-II devices support all the mandatory boundary-
scan instructions specified in the IEEE standard 1149.1. A
Test Access Port (TAP) and registers are provided that
implement the EXTEST, SAMPLE/PRELOAD, and BYPASS
instructions. The TAP also supports two USERCODE
instructions and internal scan chains.
GCLKBUF1
GCLKPAD1
GCLKBUF0
GCLKPAD0
The TAP uses dedicated package pins that always operate
using LVTTL. For TDO to operate using LVTTL, the VCCO
for Bank 2 must be 3.3V. Otherwise, TDO switches
rail-to-rail between ground and VCCO. TDI, TMS, and TCK
have a default internal weak pull-up resistor, and TDO has
no default resistor. Bitstream options allow setting any of
the four TAP pins to have an internal pull-up, pull-down, or
neither.
DS001_08_060100
Figure 8: Global Clock Distribution Network
Delay-Locked Loop (DLL)
Associated with each global clock input buffer is a fully
digital Delay-Locked Loop (DLL) that can eliminate skew
between the clock input pad and internal clock-input pins
throughout the device. Each DLL can drive two global clock
DS001-2 (v2.8) June 13, 2008
Product Specification
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