R
Spartan-II FPGA Family: Functional Description
Similarly, the F6 multiplexer combines the outputs of all four
function generators in the CLB by selecting one of the
F5-multiplexer outputs. This permits the implementation of
any 6-input function, an 8:1 multiplexer, or selected
functions of up to 19 inputs.
Each block RAM cell, as illustrated in Figure 5, is a fully
synchronous dual-ported 4096-bit RAM with independent
control signals for each port. The data widths of the two
ports can be configured independently, providing built-in
bus-width conversion.
Each CLB has four direct feedthrough paths, one per LC.
These paths provide extra data input lines or additional
local routing that does not consume logic resources.
RAMB4_S#_S#
WEA
ENA
RSTA
Arithmetic Logic
DOA[#:0]
CLKA
ADD[#:0]
DIA[#:0]
Dedicated carry logic provides capability for high-speed
arithmetic functions. The Spartan-II FPGA CLB supports
two separate carry chains, one per slice. The height of the
carry chains is two bits per CLB.
WEB
ENB
RSTB
CLKB
ADDRB[#:0]
DIB[#:0]
The arithmetic logic includes an XOR gate that allows a
1-bit full adder to be implemented within an LC. In addition,
a dedicated AND gate improves the efficiency of multiplier
implementation.
DOB[#:0]
The dedicated carry path can also be used to cascade
function generators for implementing wide logic functions.
DS001_05_060100
BUFTs
Figure 5: Dual-Port Block RAM
Each Spartan-II FPGA CLB contains two 3-state drivers
(BUFTs) that can drive on-chip busses. See "Dedicated
Routing," page 12. Each Spartan-II FPGA BUFT has an
independent 3-state control pin and an independent input
pin.
Table 6 shows the depth and width aspect ratios for the
block RAM.
Table 6: Block RAM Port Aspect Ratios
Width
Depth
4096
2048
1024
512
ADDR Bus
ADDR<11:0>
ADDR<10:0>
ADDR<9:0>
ADDR<8:0>
ADDR<7:0>
Data Bus
DATA<0>
Block RAM
1
2
Spartan-II FPGAs incorporate several large block RAM
memories. These complement the distributed RAM
Look-Up Tables (LUTs) that provide shallow memory
structures implemented in CLBs.
DATA<1:0>
DATA<3:0>
DATA<7:0>
DATA<15:0>
4
8
Block RAM memory blocks are organized in columns. All
Spartan-II devices contain two such columns, one along
each vertical edge. These columns extend the full height of
the chip. Each memory block is four CLBs high, and
consequently, a Spartan-II device eight CLBs high will
contain two memory blocks per column, and a total of four
blocks.
16
256
The Spartan-II FPGA block RAM also includes dedicated
routing to provide an efficient interface with both CLBs and
other block RAMs.
Programmable Routing Matrix
Table 5: Spartan-II Block RAM Amounts
It is the longest delay path that limits the speed of any
worst-case design. Consequently, the Spartan-II routing
architecture and its place-and-route software were defined
in a single optimization process. This joint optimization
minimizes long-path delays, and consequently, yields the
best system performance.
Spartan-II
Device
Total Block RAM
Bits
# of Blocks
XC2S15
XC2S30
XC2S50
XC2S100
XC2S150
XC2S200
4
6
16K
24K
32K
40K
48K
56K
The joint optimization also reduces design compilation
times because the architecture is software-friendly. Design
cycles are correspondingly reduced due to shorter design
iteration times.
8
10
12
14
DS001-2 (v2.8) June 13, 2008
Product Specification
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