R
QPro Virtex 2.5V QML High-Reliability FPGAs
Calculation of T
ioop
as a Function of Capacitance
The values for T
ioop
were based on the standard capacitive
load (Csl) for each I/O standard as listed in
For other capacitive loads, use the formulas below to calcu-
late the corresponding T
ioop
:
T
ioop
= T
ioopl
+ T
opadjust
+ (C
load
- C
sl
) * fl
Where:
T
opadjust
is reported above in the Output Delay
Adjustment section.
C
load
is the capacitive load for the design.
Table 2:
Constants for Use in Calculation of T
op
Standard
LVTTL slow
slew rate
2 mA drive
4 mA drive
6 mA drive
8 mA drive
12 mA drive
16 mA drive
24 mA drive
LVTTL fast
slew rate
2 mA drive
4 mA drive
6 mA drive
8 mA drive
12 mA drive
16 mA drive
24 mA drive
C
sl
(pF)
35
35
35
35
35
35
35
35
35
35
35
35
35
35
fl (ns/pF)
0.41
0.20
0.100
0.086
0.058
0.050
0.048
0.41
0.20
0.13
0.079
0.044
0.043
0.033
Table 2:
Constants for Use in Calculation of T
op
Standard
LVCMOS2
PCI 33 MHz 5V
PCI 33 MHZ 3.3V
GTL
GTL+
HSTL Class I
HSTL Class III
HSTL Class IV
SSTL2 Class I
SSTL2 Class II
SSTL3 Class 1
SSTL3 Class II
CTT
AGP
C
sl
(pF)
35
50
10
0
0
20
20
20
30
30
30
30
20
10
fl (ns/pF)
0.041
0.050
0.050
0.014
0.017
0.022
0.016
0.014
0.028
0.016
0.029
0.016
0.035
0.037
Clock Distribution Guidelines and Switching Characteristics
Speed Grade
-4
Symbol
Global Clock Skew
Description
Global clock skew between IOB flip-flops
Device
XQV100
XQV300
XQV600
XQV1000
Min
-
-
-
-
-
-
Max
0.15
0.18
0.17
0.25
0.9
0.9
Units
ns
ns
ns
ns
ns
ns
T
GSKEWIOB
T
GPIO
T
GIO
Global clock PAD to output
Global clock buffer I input to O output
All
All
Notes:
1. These clock-distribution delays are provided for guidance only. They reflect the delays encountered in a typical design under
worst-case conditions. Precise values for a particular design are provided by the timing analyzer.
DS002 (v1.5) December 5, 2001
Preliminary Product Specification
1-800-255-7778
9
XILINX [ XILINX, INC ]
